97 lines
3.1 KiB
Python
97 lines
3.1 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
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# Copyright (c) 2021 Michael T. Mayers <michael@tweakoz.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("L17"), IOStandard("LVCMOS33")),
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# Buttons
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("cpu_reset", 0, Pins("A18"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("B18"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("A17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C16"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("C17")),
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Subsignal("g", Pins("B16")),
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Subsignal("b", Pins("B17")),
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IOStandard("LVCMOS33"),
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),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("J18")),
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Subsignal("rx", Pins("J17")),
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IOStandard("LVCMOS33")),
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# SRAM
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("issiram", 0,
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Subsignal("addr", Pins(
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"M18 M19 K17 N17 P17 P18 R18 W19",
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"U19 V19 W18 T17 T18 U17 U18 V16",
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"W16 W17 V15"),
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IOStandard("LVCMOS33")),
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Subsignal("data", Pins(
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"W15 W13 W14 U15 U16 V13 V14 U14"),
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IOStandard("LVCMOS33")),
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Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
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Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
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Misc("SLEW=FAST"),
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("K19")),
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Subsignal("clk", Pins("E19")),
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Subsignal("mosi", Pins("D18")),
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Subsignal("miso", Pins("D19")),
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Subsignal("wp", Pins("G18")),
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Subsignal("hold", Pins("F18")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("K19")),
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Subsignal("clk", Pins("E19")),
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Subsignal("dq", Pins("D18 D19 G18 F18")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35tcpg236-1"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a15t.bit" if "xc7a15t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self,fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)
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