93 lines
3.5 KiB
Python
Executable File
93 lines
3.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecp5_evn
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, x5_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# clk / rst
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clk = clk12 = platform.request("clk12")
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rst_n = platform.request("rst_n")
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if x5_clk_freq is not None:
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clk = clk50 = platform.request("ext_clk50")
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self.comb += platform.request("ext_clk50_en").eq(1)
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platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk, x5_clk_freq or 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs):
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platform = ecp5_evn.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ECP5 Evaluation Board",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
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self.submodules.crg = crg
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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x5_clk_freq = args.x5_clk_freq,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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