129 lines
5.0 KiB
Python
129 lines
5.0 KiB
Python
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 David Corrigan <davidcorrigan714@gmail.com>
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# Copyright (c) 2020 Alan Green <avg@google.com>
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# Copyright (c) 2020 David Shah <dave@ds0.me>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import crosslink_nx_vip
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from litex_boards.platforms import crosslink_nx_vip
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from litehyperbus.core.hyperbus import HyperRAM
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from litex.soc.cores.nxlram import NXLRAM
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.build.io import CRG
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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# TODO: replace with PLL
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# Clocking
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self.submodules.sys_clk = sys_osc = NXOSCA()
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sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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rst_n = platform.request("gsrn")
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# Power On Reset
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por_cycles = 4096
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por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
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self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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SoCCore.mem_map = {
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"rom": 0x00000000,
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"sram": 0x40000000,
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"csr": 0xf0000000,
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}
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def __init__(self, sys_clk_freq, hyperram="none", **kwargs):
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platform = crosslink_nx_vip.Platform()
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platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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# SoCCore -----------------------------------------_----------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Crosslink-NX VIP Input Board",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if hyperram == "none":
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# 128KB LRAM (used as SRAM) ------------------------------------------------------------
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size = 128*kB
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self.submodules.spram = NXLRAM(32, size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
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else:
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# Use HyperRAM generic PHY as SRAM -----------------------------------------------------
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size = 8*1024*kB
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hr_pads = platform.request("hyperram", int(hyperram))
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self.submodules.hyperram = HyperRAM(hr_pads)
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self.register_mem("sram", self.mem_map["sram"], self.hyperram.bus, size)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip 0 or 1 (default=none)")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
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parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), hyperram=args.with_hyperram, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target)
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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