58 lines
2.0 KiB
Python
58 lines
2.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# https://www.crowdsupply.com/fairwaves/xtrx
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk/Rst.
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("clk60", 0, Pins("C16"), IOStandard("LVCMOS25")),
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# Leds.
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("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("B8")),
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Subsignal("clk_n", Pins("A8")),
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Subsignal("rx_p", Pins("B10")),
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Subsignal("rx_n", Pins("A10")),
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Subsignal("tx_p", Pins("B6")),
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Subsignal("tx_n", Pins("A6")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk60"
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default_clk_period = 1e9/60e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk60", loose=True), 1e9/60e6)
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