Gwenhael Goavec-Merou b1a6da84b3 sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module		2024-08-04 12:14:56 +02:00
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platforms	sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module	2024-08-04 12:14:56 +02:00
prog	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
targets	sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module	2024-08-04 12:14:56 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00