116 lines
5.2 KiB
Python
116 lines
5.2 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("AB11"), IOStandard("LVDS")),
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Subsignal("n", Pins("AC11"), IOStandard("LVDS"))
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),
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("cpu_reset_n", 0, Pins("G9"), IOStandard("LVCMOS25")),
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# Leds
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("user_led", 0, Pins("U9"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 1, Pins("V12"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 2, Pins("V13"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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("user_led", 3, Pins("W13"), IOStandard("LVCMOS15"), Misc("SLEW=SLOW")),
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# The Serial which connects to the second UART
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# of the FTDI on the base board (first FTDI port is JTAG)
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("serial", 0,
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Subsignal("tx", Pins("A20")),
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Subsignal("rx", Pins("B20")),
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IOStandard("LVCMOS15")
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),
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# Serial This one is multiplexed with the I2C bus
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("serial", 1,
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Subsignal("tx", Pins("W11")),
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Subsignal("rx", Pins("AB16")),
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IOStandard("LVCMOS15")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AE11 AF9 AD10 AB10 AA9 AB9 AA8 AC8",
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"AA7 AE8 AF10 AD8 AE10 AF8 AC7"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AD11 AA10 AF12"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AE13"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE12"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA12"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("Y12"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"Y3 U5 AD4 AC4 AF19 AC16 AB19 V14"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AA2 Y2 AB2 V1 Y1 W1 AC2 V2",
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"W3 V3 U1 U7 U6 V4 V6 U2",
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"AE3 AE6 AF3 AD1 AE1 AE2 AF2 AE5",
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"AD5 Y5 AC6 Y6 AB4 AD6 AB6 AC3",
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"AD16 AE17 AF15 AF20 AD15 AF14 AE15 AF17",
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"AA14 AA15 AC14 AD14 AB14 AB15 AA17 AA18",
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"AB20 AD19 AC19 AA20 AA19 AC17 AD18 AB17",
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"W15 W16 W14 V16 V19 V17 V18 Y17"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AB1 W6 AF5 AA5 AE18 Y15 AD20 W18"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("dqs_n", Pins("AC1 W5 AF4 AB5 AF18 Y16 AE20 W19"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("clk_p", Pins("AB12"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AC12"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AA13"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AD13"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15"), Misc("SLEW=SLOW")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH"),
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),
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# Don't use, this is for documentation only.
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# This pin sets DDR3 voltage. LOW = 1.3V, HI-Z = 1.5V, HIGH = illegal
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("ddram_vsel", 0, Pins('AA3'), IOStandard("SSTL15"), Misc("SLEW=SLOW")),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xc7k160tffg676-2", _io, toolchain=toolchain)
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property CFGBVS GND [current_design]")
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# DDR3 is connected to banks 32, 33 and 34
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 32]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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# The VRP/VRN resistors are connected to bank 34.
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# Banks 32 and 33 have LEDs in the places, so we have to use the reference from bank 34
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# Bank 33 has no _T_DCI signals connected
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self.add_platform_command("set_property DCI_CASCADE {{32}} [get_iobanks 34]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]")
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# Important! Do not remove this constraint!
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# This property ensures that all unused pins are set to high impedance.
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# If the constraint is removed, all unused pins have to be set to HiZ in the top level file
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# This causes DDR3 to use 1.5V by default
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) |