56 lines
1.8 KiB
Python
56 lines
1.8 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("rst", 0, Pins("G13"), IOStandard("LVCMOS18")),
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("clk125", 0,
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Subsignal("p", Pins("H9"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("G9"), IOStandard("DIFF_SSTL15")),
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),
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# Leds
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("user_led", 0, Pins("AL11"), IOStandard("LVCMOS12")),
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("user_led", 1, Pins("AL13"), IOStandard("LVCMOS12")),
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("user_led", 2, Pins("AK13"), IOStandard("LVCMOS12")),
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("user_led", 3, Pins("AE15"), IOStandard("LVCMOS12")),
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("user_led", 4, Pins("AM8"), IOStandard("LVCMOS12")),
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("user_led", 5, Pins("AM9"), IOStandard("LVCMOS12")),
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("user_led", 6, Pins("AM10"), IOStandard("LVCMOS12")),
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("user_led", 7, Pins("AM11"), IOStandard("LVCMOS12")),
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# Serial
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("serial", 0,
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Subsignal("cts", Pins("AP17")),
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Subsignal("rts", Pins("AM15")),
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Subsignal("tx", Pins("AL17")),
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Subsignal("rx", Pins("AH17")),
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IOStandard("LVCMOS12")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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