mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
178 lines
8 KiB
Python
Executable file
178 lines
8 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
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# SPDX-License-Identifier: BSD-2-Clause
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# Testing build for HDMI
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# - The main trouble with HDMI demos are that they require many SLICEMs, which are a very limited
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# resource on the XC6SLX9. Many of these examples are just trying to reduce usage of them.
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#
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# # Simple colorbar output
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# ./alchitry_mojo.py \
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# --build \
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# --with-hdmi-shield \
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# --with-video-colorbars \
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# --csr-csv=build/alchitry_mojo/csr.csv
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#
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# # Video Terminal (lower SRAM size to allow for text buffer)
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# ./alchitry_mojo.py \
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# --build \
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# --with-hdmi-shield \
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# --with-video-terminal \
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# --csr-csv=build/alchitry_mojo/csr.csv \
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# --integrated-rom-size 32768 \
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# --integrated-sram-size 4096
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#
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# # Video Framebuffer (double sdram speed to have enough bandwidth)
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# # Lower the fifo_depth in litex/litex/soc/cores/video.py "class VideoFrameBuffer" to 1024
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# ./alchitry_mojo.py \
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# --build \
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# --with-hdmi-shield \
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# --with-video-framebuffer \
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# --csr-csv=build/alchitry_mojo/csr.csv \
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# --integrated-rom-size 32768 \
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# --sdram-rate 1:2
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#
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# litex> # Turn screen Red
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# litex> mem_write 0x40c00000 0xffff0000 307200
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from migen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import alchitry_mojo
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.video import VideoS6HDMIPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC32M8, SDRModule
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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else:
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self.clock_domains.cd_sys_ps = ClockDomain()
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# Clk/Rst
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clk50 = platform.request("clk50")
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rst = platform.request("cpu_reset")
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avr_ready = platform.request("cclk")
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# PLL
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self.submodules.pll = pll = S6PLL()
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self.comb += pll.reset.eq(~rst | ~avr_ready | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(62.5e6), sdram_rate="1:1", with_hdmi_shield=False,
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with_sdram_shield=False, with_led_chaser=True, with_video_terminal=False,
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with_video_framebuffer=False, with_video_colorbars=False, **kwargs):
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platform = alchitry_mojo.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq, sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alchitry Mojo", **kwargs)
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# HDMI Shield ------------------------------------------------------------------------------
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if with_hdmi_shield:
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self.platform.add_extension(alchitry_mojo._hdmi_shield)
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# SDRAM Shield -----------------------------------------------------------------------------
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if with_sdram_shield:
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self.platform.add_extension(alchitry_mojo._sdram_shield)
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# Add SDRAM if a shield with RAM has been added
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if not self.integrated_main_ram_size and (with_hdmi_shield or with_sdram_shield):
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.crg.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC32M8(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 1024)
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)
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# HDMI Options -----------------------------------------------------------------------------
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if with_hdmi_shield and (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.submodules.videophy = VideoS6HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Mojo")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--sys-clk-freq", default=62.5e6, help="System clock frequency.")
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target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
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shields1 = target_group.add_mutually_exclusive_group()
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shields1.add_argument("--with-hdmi-shield", action="store_true", help="Enable HDMI Shield.")
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shields1.add_argument("--with-sdram-shield", action="store_true", help="Enable SDRAM Shield.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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# Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
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# set to a fixed rate of 500 kilobaud.
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sdram_rate = args.sdram_rate,
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with_hdmi_shield = args.with_hdmi_shield,
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with_sdram_shield = args.with_sdram_shield,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_colorbars = args.with_video_colorbars,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if __name__ == "__main__":
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main()
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