mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
137 lines
5.2 KiB
Python
Executable file
137 lines
5.2 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use ----------------------------------------------------------------------------------------
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# Build/Flash bitstream:
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# ./fairwaves_xtrx.py --uart-name=crossover --with-pcie --build --driver --flash
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#
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#.Build the kernel and load it:
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# cd build/<platform>/driver/kernel
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# make
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# sudo ./init.sh
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#
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# Test userspace utilities:
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# cd build/<platform>/driver/user
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# make
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# ./litepcie_util info
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# ./litepcie_util scratch_test
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# ./litepcie_util dma_test
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# ./litepcie_util uart_test
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import os
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from migen import *
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from litex_boards.platforms import fairwaves_xtrx
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.clock import *
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_pcie=False):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if with_pcie:
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assert sys_clk_freq == int(125e6)
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self.comb += [
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self.cd_sys.clk.eq(ClockSignal("pcie")),
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self.cd_sys.rst.eq(ResetSignal("pcie")),
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]
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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pll.register_clkin(platform.request("clk60"), 60e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs):
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platform = fairwaves_xtrx.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq, with_pcie)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Fairwaves XTRX", **kwargs)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"),
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data_width = 64,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# ICAP (For FPGA reload over PCIe).
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from litex.soc.cores.icap import ICAP
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self.submodules.icap = ICAP()
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self.icap.add_reload()
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# Flash (For SPIFlash update over PCIe).
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.spi_flash import S7SPIFlash
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self.submodules.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
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self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Fairwaves XTRX")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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