mirror of
https://github.com/litex-hub/litex-boards.git
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a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
97 lines
3.8 KiB
Python
Executable file
97 lines
3.8 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Michael Welling <mwelling@ieee.org>
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# Copyright (c) 2020 Sean Cross <sean@xobs.io>
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# Copyright (c) 2020 Drew Fustini <drew@pdp7.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import hadbadge
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY
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from litedram.modules import AS4C32M8
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk8 = platform.request("clk8")
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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pll.pfd_freq_range = (8e6, 400e6) # Lower Min from 10MHz to 8MHz.
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk8, 8e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
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platform = hadbadge.Platform(toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Hackaday Badge", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = AS4C32M8(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Hackaday Badge")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if __name__ == "__main__":
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main()
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