mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
267 lines
11 KiB
Python
Executable file
267 lines
11 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecpix5
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import MT41K256M16
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk100)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI = self.cd_sys2x_i.clk,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, device="85F", sys_clk_freq=int(75e6),
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with_ethernet = False,
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with_etherbone = False,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_led_chaser = True,
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**kwargs):
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platform = ecpix5.Platform(device=device, toolchain="trellis")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K256M16(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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rx_delay = 0e-9)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# HDMI -------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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# PHY + IT6613 I2C initialization.
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hdmi_pads = platform.request("hdmi")
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self.submodules.videophy = VideoDVIPHY(hdmi_pads, clock_domain="init")
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self.submodules.videoi2c = I2CMaster(hdmi_pads)
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# I2C initialization adapted from https://github.com/ultraembedded/ecpix-5
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# Copyright (c) 2020 https://github.com/ultraembedded
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# Adapted from C to Python.
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REG_TX_SW_RST = 0x04
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B_ENTEST = (1<<7)
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B_REF_RST = (1<<5)
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B_AREF_RST = (1<<4)
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B_VID_RST = (1<<3)
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B_AUD_RST = (1<<2)
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B_HDMI_RST = (1<<1)
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B_HDCP_RST = (1<<0)
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REG_TX_AFE_DRV_CTRL = 0x61
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B_AFE_DRV_PWD = (1<<5)
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B_AFE_DRV_RST = (1<<4)
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B_AFE_DRV_PDRXDET = (1<<2)
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B_AFE_DRV_TERMON = (1<<1)
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B_AFE_DRV_ENCAL = (1<<0)
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REG_TX_AFE_XP_CTRL = 0x62
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B_AFE_XP_GAINBIT = (1<<7)
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B_AFE_XP_PWDPLL = (1<<6)
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B_AFE_XP_ENI = (1<<5)
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B_AFE_XP_ER0 = (1<<4)
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B_AFE_XP_RESETB = (1<<3)
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B_AFE_XP_PWDI = (1<<2)
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B_AFE_XP_DEI = (1<<1)
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B_AFE_XP_DER = (1<<0)
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REG_TX_AFE_ISW_CTRL = 0x63
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B_AFE_RTERM_SEL = (1<<7)
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B_AFE_IP_BYPASS = (1<<6)
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M_AFE_DRV_ISW = (7<<3)
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O_AFE_DRV_ISW = 3
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B_AFE_DRV_ISWK = 7
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REG_TX_AFE_IP_CTRL = 0x64
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B_AFE_IP_GAINBIT = (1<<7)
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B_AFE_IP_PWDPLL = (1<<6)
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M_AFE_IP_CKSEL = (3<<4)
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O_AFE_IP_CKSEL = 4
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B_AFE_IP_ER0 = (1<<3)
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B_AFE_IP_RESETB = (1<<2)
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B_AFE_IP_ENC = (1<<1)
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B_AFE_IP_EC1 = (1<<0)
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REG_TX_HDMI_MODE = 0xC0
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B_TX_HDMI_MODE = 1
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B_TX_DVI_MODE = 0
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REG_TX_GCP = 0xC1
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B_CLR_AVMUTE = 0
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B_SET_AVMUTE = 1
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B_TX_SETAVMUTE = (1<<0)
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B_BLUE_SCR_MUTE = (1<<1)
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B_NODEF_PHASE = (1<<2)
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B_PHASE_RESYNC = (1<<3)
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self.videoi2c.add_init(addr=0x4c, init=[
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# Reset.
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(REG_TX_SW_RST, B_REF_RST | B_VID_RST | B_AUD_RST | B_AREF_RST | B_HDCP_RST),
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(REG_TX_SW_RST, 0),
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# Select DVI Mode.
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(REG_TX_HDMI_MODE, B_TX_DVI_MODE),
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# Configure Clks.
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(REG_TX_SW_RST, B_AUD_RST | B_AREF_RST | B_HDCP_RST),
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(REG_TX_AFE_DRV_CTRL, B_AFE_DRV_RST),
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(REG_TX_AFE_XP_CTRL, 0x18),
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(REG_TX_AFE_ISW_CTRL, 0x10),
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(REG_TX_AFE_IP_CTRL, 0x0C),
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# Enable Clks.
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(REG_TX_AFE_DRV_CTRL, 0),
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# Enable Video.
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(REG_TX_GCP, 0),
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])
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# Video Terminal/Framebuffer.
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="init")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="init")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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leds_pads = []
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for i in range(4):
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rgb_led_pads = platform.request("rgb_led", i)
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self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds.
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leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
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self.submodules.leds = LedChaser(
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pads = Cat(leds_pads),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ECPIX-5")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
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target_group.add_argument("--device", default="85F", help="ECP5 device (45F or 85F).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(None, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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