mirror of
https://github.com/litex-hub/litex-boards.git
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a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
210 lines
8.7 KiB
Python
Executable file
210 lines
8.7 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# Copyright (c) 2022 Martin Hubacek @hubmartin (Twitter)
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecp5_vip
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K64M16
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from litedram.phy import ECP5DDRPHY
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.bitbang import I2CMaster
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk100)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI = self.cd_sys2x_i.clk,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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# HDMI
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self.clock_domains.cd_hdmi = ClockDomain()
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#pll.create_clkout(self.cd_hdmi, 148.5e6) # for terminal "1920x1080@60Hz"
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#pll.create_clkout(self.cd_hdmi, 160e6) # for terminal "1920x1080@60Hz"
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#pll.create_clkout(self.cd_hdmi, 80e6) # for terminal "1920x1080@30Hz"
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pll.create_clkout(self.cd_hdmi, 40e6) # for terminal "800x600@60Hz"
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
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with_led_chaser = True,
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with_video_terminal = True,
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with_video_framebuffer = False,
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**kwargs):
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platform = ecp5_vip.Platform(toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c)
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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pads = platform.request("hdmi")
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self.submodules.videophy = VideoVGAPHY(pads, clock_domain="hdmi")
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self.submodules.videoi2c = I2CMaster(pads)
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# # 1920x1080@60Hz
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# pixel_clock_hz = 160e6
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# framerate_hz = 60
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# pixels_horizontal = 2200
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# pixels_vertical = 1125
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# 800x600@60Hz
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pixel_clock_hz = 40e6
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framerate_hz = 60
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pixels_horizontal = 1056
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pixels_vertical = 628
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# # 1920x1080@30Hz
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# pixel_clock_hz = 80e6
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# framerate_hz = 30
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# pixels_horizontal = 2640
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# pixels_vertical = 1125
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self.videoi2c.add_init(addr=0x3B, init=[
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(0xc7, 0x00), # HDMI configuration
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(0xc7, 0x00), # Write twice, the first transfer fails for some reason
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(0x1e, 0x00), # Power up transmitter
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(0x08, 0x60), # Input Bus/Pixel Repetition (default)
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(0x00, int((pixel_clock_hz/1e4) %256)), # Pixel clock in MHz * 100
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(0x01, int((pixel_clock_hz/1e4)//256)), #
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(0x02, int((framerate_hz*100) %256)), # Framerate * 100
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(0x03, int((framerate_hz*100)//256)), #
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(0x04, int((pixels_horizontal) %256)), # Pixels horizontal
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(0x05, int((pixels_horizontal)//256)), #
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(0x06, int((pixels_vertical) %256)), # Pixels vertical
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(0x07, int((pixels_vertical)//256)), #
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(0x1a, 0x00) # end
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])
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if with_video_terminal:
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#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="1920x1080@30Hz", clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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#self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Running code from SPI flash had some side effects on BIOS with enabled DDR3 memory
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# So I reverted to the FPGA BRAM for BIOS.
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# # SPI Flash --------------------------------------------------------------------------------
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# from litespi.modules import MX25L12835F
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# from litespi.opcodes import SpiNorFlashOpCodes as Codes
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# self.add_spi_flash(mode="1x", module=MX25L12835F(Codes.READ_1_1_1), with_master=False)
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# # Add ROM linker region --------------------------------------------------------------------
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# self.bus.add_region("rom", SoCRegion(
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# origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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# size = (16-4)*1024*1024,
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# linker = True)
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# )
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream")
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target_group.add_argument("--load", action="store_true", help="Load bitstream")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
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if __name__ == "__main__":
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main()
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