mirror of
https://github.com/litex-hub/litex-boards.git
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a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
70 lines
2.7 KiB
Python
Executable file
70 lines
2.7 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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import importlib
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from migen import *
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from litex.build.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, platform, with_ethernet=False, with_led_chaser=True, **kwargs):
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sys_clk_freq = int(1e9/platform.default_clk_period)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX Simple SoC", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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try:
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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except:
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pass
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="Generic LiteX SoC")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("platform", help="Module name of the platform to build for.")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default=None, help="FPGA toolchain.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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platform_module = importlib.import_module(args.platform)
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platform_kwargs = {}
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if args.toolchain is not None:
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platform_kwargs["toolchain"] = args.toolchain
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platform = platform_module.Platform(**platform_kwargs)
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soc = BaseSoC(platform,**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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