107 lines
4.4 KiB
Python
Executable File
107 lines
4.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import nexys4ddr
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT47H64M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_eth, 50e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
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platform = nexys4ddr.Platform()
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# SoCCore ----------------------------------_-----------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR2 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR2",
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nphases = 2,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT47H64M16(sys_clk_freq, "1:2"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
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with_ethernet=args.with_ethernet,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
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if __name__ == "__main__":
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main()
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