155 lines
6.4 KiB
Python
Executable File
155 lines
6.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import ac701
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = ac701.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, phy="rgmii", **kwargs):
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assert phy in ["rgmii", "1000basex"]
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BaseSoC.__init__(self, **kwargs)
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# RGMII Ethernet PHY -----------------------------------------------------------------------
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if phy == "rgmii":
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.add_csr("ethphy")
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# 1000BaseX Ethernet PHY -------------------------------------------------------------------
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if phy == "1000basex":
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self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
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self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
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qpll_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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refclk125 = self.platform.request("gtp_refclk")
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refclk125_se = Signal()
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self.specials += \
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=refclk125.p,
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i_IB=refclk125.n,
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o_O=refclk125_se)
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qpll = QPLL(refclk125_se, qpll_settings)
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self.submodules += qpll
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self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq)
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self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6)
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self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.txoutclk,
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self.ethphy.rxoutclk)
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# Ethernet MAC -----------------------------------------------------------------------------
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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parser.add_argument("--ethernet-phy", default="rgmii",
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help="select Ethernet PHY (rgmii or 1000basex)")
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args = parser.parse_args()
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if args.with_ethernet:
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soc = EthernetSoC(args.ethernet_phy, **soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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