113 lines
4.1 KiB
Python
Executable File
113 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import de1soc
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import IS42S16320
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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platform.add_period_constraint(clk50, 1e9/50e6)
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# PLL
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pll_locked = Signal()
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pll_clk_out = Signal(6)
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self.specials += \
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Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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p_CLK0_DIVIDE_BY = 1,
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p_CLK0_DUTY_CYCLE = 50,
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p_CLK0_MULTIPLY_BY = 1,
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p_CLK0_PHASE_SHIFT = "0",
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p_CLK1_DIVIDE_BY = 1,
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p_CLK1_DUTY_CYCLE = 50,
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p_CLK1_MULTIPLY_BY = 1,
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p_CLK1_PHASE_SHIFT = "-10000",
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p_COMPENSATE_CLOCK = "CLK0",
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p_INCLK0_INPUT_FREQUENCY = 20000,
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p_OPERATION_MODE = "NORMAL",
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i_INCLK = clk50,
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o_CLK = pll_clk_out,
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i_ARESET = 0,
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i_CLKENA = 0x3f,
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i_EXTCLKENA = 0xf,
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i_FBIN = 1,
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i_PFDENA = 1,
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i_PLLENA = 1,
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o_LOCKED = pll_locked,
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)
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self.comb += [
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self.cd_sys.clk.eq(pll_clk_out[0]),
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self.cd_sys_ps.clk.eq(pll_clk_out[1]),
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
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]
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de1soc.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = IS42S16320(sys_clk_freq, "1:1"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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