100 lines
3.8 KiB
Python
Executable File
100 lines
3.8 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Fei Gao <feig@princeton.edu>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 David Shah <dave@ds0.me>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import alveo_u250
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk500 = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(0)
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pll.register_clkin(platform.request("clk300", 0), 300e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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platform = alveo_u250.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6,
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cmd_latency = 1,
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is_rdimm = True)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY_DEBUG")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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self.add_ram("firmware_ram", 0x20000000, 0x8000)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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