155 lines
5.4 KiB
Python
Executable File
155 lines
5.4 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Michael T. Mayers <michael@tweakoz.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.build.io import CRG
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from litex_boards.platforms import micronova_mercury2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import colorer
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# _CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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# # #
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pll_clk50 = platform.request("clk50")
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self.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(pll_clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# AsyncSRAM ------------------------------------------------------------------------------------------
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class AsyncSRAM(LiteXModule):
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def __init__(self, platform, size):
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addr_width = size//8
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data_width = 8
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self.bus = wishbone.Interface(data_width=data_width,adr_width=addr_width)
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issiram = platform.request("issiram")
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addr = issiram.addr
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data = issiram.data
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wen = issiram.wen
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cen = issiram.cen
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########################
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tristate_data = TSTriple(data_width)
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self.specials += tristate_data.get_tristate(data)
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########################
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chip_ena = self.bus.cyc & self.bus.stb & self.bus.sel[0]
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write_ena = (chip_ena & self.bus.we)
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########################
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# external write enable,
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# external chip enable,
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# internal tristate write enable
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########################
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self.comb += [
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cen.eq(~chip_ena),
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wen.eq(~write_ena),
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tristate_data.oe.eq(write_ena)
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]
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########################
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# address and data
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########################
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self.comb += [
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addr.eq(self.bus.adr[:addr_width]),
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self.bus.dat_r.eq(tristate_data.i[:data_width]),
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tristate_data.o.eq(self.bus.dat_w[:data_width])
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]
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########################
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# generate ack
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########################
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self.sync += [
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self.bus.ack.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack),
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]
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########################
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def addAsyncSram(soc, platform, name, origin, size):
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ram_bus = wishbone.Interface(data_width=soc.bus.data_width)
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ram = AsyncSRAM(platform,size)
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soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw"))
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soc.check_if_exists(name)
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soc.logger.info("ISSIRAM {} {} {}.".format(
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colorer(name),
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colorer("added", color="green"),
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soc.bus.regions[name]))
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setattr(soc.submodules, name, ram)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self,
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variant = "a7-35",
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toolchain = "vivado",
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sys_clk_freq = 100e6,
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with_led_chaser = True,
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**kwargs):
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platform = micronova_mercury2.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MicroNova Mercury2", **kwargs)
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# Async RAM --------------------------------------------------------------------------------
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addAsyncSram(self,platform,"main_ram", 0x40000000, 512*1024)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=micronova_mercury2.Platform, description="LiteX SoC on MicroNova Mercury2.")
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parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder_argd = parser.builder_argdict
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builder = Builder(soc, **builder_argd)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if __name__ == "__main__":
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main()
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