215 lines
8.3 KiB
Python
Executable File
215 lines
8.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Pepijn de Vos <pepijndevos@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import importlib
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from migen import *
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from litex.build.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import tec0117
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from litedram.modules import MT48LC4M16 # FIXME: use EtronTech reference.
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Generate 25Mhz sys_clk_freq clock from 100MHz input clock, FIXME: use PLL.
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assert sys_clk_freq == 25e6
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self.clock_domains.cd_clk100 = ClockDomain()
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self.comb += self.cd_clk100.clk.eq(clk100)
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count = Signal(2)
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self.sync.clk100 += count.eq(count + 1)
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clk50 = count[0]
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clk25 = count[1]
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self.comb += self.cd_sys.clk.eq(clk25)
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self.comb += self.cd_sys.rst.eq(~rst_n | self.rst) # FIXME: use AsyncResetSynchronizer
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1", **kwargs):
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platform = tec0117.Platform()
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# Use custom default configuration to fit in LittleBee.
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kwargs["integrated_sram_size"] = 0x1000
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kwargs["integrated_rom_size"] = 0x6000
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kwargs["cpu_type"] = "vexriscv"
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kwargs["cpu_variant"] = "lite"
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on TEC0117",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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# Add ROM linker region --------------------------------------------------------------------
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# FIXME: SPI Flash does not seem responding, power down set after loading bitstream?
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#self.bus.add_region("rom", SoCRegion(
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# origin = self.mem_map["spiflash"] + bios_flash_offset,
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# size = 32*kB,
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# linker = True)
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#)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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class SDRAMPads:
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def __init__(self):
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self.clk = platform.request("O_sdram_clk")
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self.cke = platform.request("O_sdram_cke")
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self.cs_n = platform.request("O_sdram_cs_n")
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self.cas_n = platform.request("O_sdram_cas_n")
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self.ras_n = platform.request("O_sdram_ras_n")
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self.we_n = platform.request("O_sdram_wen_n")
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self.dm = platform.request("O_sdram_dqm")
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self.a = platform.request("O_sdram_addr")
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self.ba = platform.request("O_sdram_ba")
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self.dq = platform.request("IO_sdram_dq")
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sdram_pads = SDRAMPads()
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self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) # FIXME: use phase shift from PLL.
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
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origin = self.mem_map["main_ram"],
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l2_cache_size = 128,
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l2_cache_min_data_width = 256,
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset):
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# Prepare Flash image.
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# --------------------
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bitstream = open("build/tec0117/gateware/impl/pnr/project.bin", "rb")
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bios = open("build/tec0117/software/bios/bios.bin", "rb")
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image = open("build/tec0117/image.bin", "wb")
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# Copy Bitstream at 0.
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blength = 0
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while True:
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b = bitstream.read(1)
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if not b:
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break
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else:
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image.write(b)
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blength += 1
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# Check Bitstream/BIOS overlap.
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if blength > bios_flash_offset:
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raise ValueError(f"Bitstream/BIOS overlap 0x{blength:08x} vs 0x{bios_flash_offset:08x}, increase BIOS Flash offset.")
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# Fill Gap between Bitstream/BIOS with zeroes.
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for i in range(bios_flash_offset - blength):
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image.write(0x00.to_bytes(1, "big"))
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# Copy BIOS at bios_flash_offset
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while True:
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b = bios.read(1)
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if not b:
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break
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else:
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image.write(b)
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# Create FTDI <--> SPI Flash proxy bitstream and load it.
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# -------------------------------------------------------
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platform = tec0117.Platform()
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flash = platform.request("spiflash", 0)
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bus = platform.request("spiflash", 1)
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module = Module()
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module.comb += [
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flash.clk.eq(bus.clk),
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flash.cs_n.eq(bus.cs_n),
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flash.mosi.eq(bus.mosi),
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bus.miso.eq(flash.miso),
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]
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platform.build(module)
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prog = platform.create_programmer()
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prog.load_bitstream("build/impl/pnr/project.fs")
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# Flash Image through proxy Bitstream.
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# ------------------------------------
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from spiflash.serialflash import SerialFlashManager
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dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
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dev.TIMINGS["chip"] = (4, 60) # Chip is too slow
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print("Erasing flash...")
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dev.erase(0, -1)
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with open("build/tec0117/image.bin", "rb") as f:
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image = f.read()
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print("Programming flash...")
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dev.write(0, image)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x80000, help="BIOS offset in SPI Flash (0x00000 default)")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS")
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parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 12MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = args.bios_flash_offset,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args), bios_options=["TERM_MINI"])
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if args.flash:
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# flash(args.bios_flash_offset) FIXME.
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if __name__ == "__main__":
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main()
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