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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
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2021-01-08 18:50:01 +01:00 |
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acorn_cle_215.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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aller.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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alveo_u250.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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arty.py
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add etherbone ip address option for relevant boards
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2021-01-08 18:44:31 +01:00 |
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arty_s7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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c10lprefkit.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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camlink_4k.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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colorlight_5a_75x.py
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targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.
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2021-01-07 09:26:38 +01:00 |
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crosslink_nx_evn.py
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nexus: Allow selection of toolchain
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2020-11-25 09:45:25 +00:00 |
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crosslink_nx_vip.py
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nexus: Allow selection of toolchain
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2020-11-25 09:45:25 +00:00 |
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de0nano.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de1soc.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de2_115.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de10lite.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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de10nano.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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ecp5_evn.py
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targets: cleanup, uniformize build arguments between targets.
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2020-11-12 11:46:00 +01:00 |
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ecpix5.py
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targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
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2020-12-29 16:01:12 +01:00 |
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fk33.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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fomu.py
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targets/fomu: modification to ValentyUSB no longer required.
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2020-11-27 19:40:45 +01:00 |
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genesys2.py
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Merge pull request #144 from gsomlo/gls-genesys2-sdcard
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2021-01-07 08:12:24 +01:00 |
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hadbadge.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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icebreaker.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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kc705.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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kcu105.py
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add etherbone ip address option for relevant boards
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2021-01-08 18:44:31 +01:00 |
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kx2.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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linsn_rv901t.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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litefury.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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logicbone.py
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target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).
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2020-11-27 18:53:45 +01:00 |
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mercury_xu5.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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mimas_a7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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minispartan6.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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mist.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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nereid.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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netv2.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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nexys4ddr.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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nexys_video.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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orangecrab.py
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orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).
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2021-01-04 09:42:05 +01:00 |
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pano_logic_g2.py
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add etherbone ip address option for relevant boards
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2021-01-08 18:44:31 +01:00 |
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pipistrello.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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qmtech_ep4ce15.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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qmtech_wukong.py
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add etherbone ip address option for relevant boards
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2021-01-08 18:44:31 +01:00 |
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redpitaya.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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sds1104xe.py
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sds1104xe: defaults to Crossover UART.
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2021-01-08 19:00:41 +01:00 |
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simple.py
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targets/simple: add try/except on leds.
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2020-11-12 14:26:00 +01:00 |
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tagus.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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tec0117.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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tinyfpga_bx.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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trellisboard.py
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targets: add --sys-clk-freq support to all targets.
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2020-11-12 18:07:28 +01:00 |
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ulx3s.py
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targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
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2021-01-04 11:38:07 +01:00 |
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vc707.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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vcu118.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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versa_ecp5.py
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add etherbone ip address option for relevant boards
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2021-01-08 18:44:31 +01:00 |
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xcu1525.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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zcu104.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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zybo_z7.py
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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