186 lines
6.3 KiB
Python
186 lines
6.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("K23"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("N5"), IOStandard("LVCMOS33")),
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# Leds
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("rgb_led", 0,
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Subsignal("r", Pins("P21")),
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Subsignal("g", Pins("R23")),
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Subsignal("b", Pins("P22")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 1,
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Subsignal("r", Pins("K21")),
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Subsignal("g", Pins("K24")),
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Subsignal("b", Pins("M21")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 2,
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Subsignal("r", Pins("U21")),
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Subsignal("g", Pins("W21")),
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Subsignal("b", Pins("T24")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 3,
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Subsignal("r", Pins("T23")),
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Subsignal("g", Pins("R21")),
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Subsignal("b", Pins("T22")),
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IOStandard("LVCMOS33"),
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),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("R26"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("R24"), IOStandard("LVCMOS33")),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"T5 M3 L3 V6 K2 W6 K3 L1",
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"H2 L2 N1 J1 M1 K1 H1"),
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IOStandard("SSTL15_I")),
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Subsignal("ba", Pins("U6 N3 N4"), IOStandard("SSTL15_I")),
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Subsignal("ras_n", Pins("T3"), IOStandard("SSTL15_I")),
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Subsignal("cas_n", Pins("P2"), IOStandard("SSTL15_I")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15_I")),
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Subsignal("dm", Pins("U4 U1"), IOStandard("SSTL15_I")),
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Subsignal("dq", Pins(
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"T4 W4 R4 W5 R6 P6 P5 P4",
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"R1 W3 T2 V3 U3 W1 T1 W2",),
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IOStandard("SSTL15_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("V4 V1"), IOStandard("SSTL15D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("H3"), IOStandard("SSTL15D_I")),
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Subsignal("cke", Pins("P1"), IOStandard("SSTL15_I")),
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Subsignal("odt", Pins("P3"), IOStandard("SSTL15_I")),
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Misc("SLEWRATE=FAST"),
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),
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# RGMII Ethernetx
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("eth_clocks", 0,
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Subsignal("tx", Pins("A12")),
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Subsignal("rx", Pins("E11")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("C13")),
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Subsignal("mdio", Pins("A13")),
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Subsignal("mdc", Pins("C11")),
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Subsignal("rx_ctl", Pins("A11")),
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Subsignal("rx_data", Pins("B11 A10 B10 A9"), Misc("PULLMODE=UP")), # RGMII mode - Advertise all capabilities.
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Subsignal("tx_ctl", Pins("C9")),
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Subsignal("tx_data", Pins("D8 C8 B8 A8")),
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IOStandard("LVCMOS33")
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),
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# SDCard
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("sdcard", 0,
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Subsignal("data", Pins("N26 N25 N23 N21"), Misc("PULLMODE=UP")),
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Subsignal("cmd", Pins("M24"), Misc("PULLMODE=UP")),
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Subsignal("clk", Pins("P24")),
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Subsignal("cd", Pins("L22")),
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Subsignal("cmd_dir", Pins("M23")),
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Subsignal("dat0_dir", Pins("N24")),
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Subsignal("dat13_dir", Pins("P26")),
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IOStandard("LVCMOS33"),
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),
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# Sata
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("sata", 0,
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Subsignal("clk_p", Pins("AF12")),
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Subsignal("clk_n", Pins("AF13")),
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Subsignal("rx_p", Pins("AF15")),
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Subsignal("rx_n", Pins("AF16")),
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Subsignal("tx_p", Pins("AD16")),
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Subsignal("tx_n", Pins("AD17")),
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IOStandard("LVCMOS33"),
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("AA2")),
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Subsignal("mosi", Pins("AE2")),
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Subsignal("miso", Pins("AD2")),
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Subsignal("wp", Pins("AF2")),
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Subsignal("hold", Pins("AE1")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("AA2")),
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Subsignal("dq", Pins("AE2", "AD2", "AF2", "AE1")),
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IOStandard("LVCMOS33")
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),
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# USB
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("ulpi", 0,
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Subsignal("rst", Pins("E23")),
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Subsignal("clk", Pins("H24")),
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Subsignal("dir", Pins("F22")),
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Subsignal("nxt", Pins("F23")),
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Subsignal("stp", Pins("H23")),
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Subsignal("data", Pins("M26 L25 L26 K25 K26 J23 P25 H25")),
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IOStandard("LVCMOS33")
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),
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# HDMI / IT6613
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("hdmi", 0,
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Subsignal("r", Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4")),
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Subsignal("g", Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6")),
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Subsignal("b", Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C8 D2 D1 E3")),
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Subsignal("de", Pins("A3")),
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Subsignal("clk", Pins("C1")),
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Subsignal("vsync", Pins("A4")),
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Subsignal("hsync", Pins("B4")),
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Subsignal("sda", Pins("E17")),
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Subsignal("scl", Pins("C17")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod0", "T25 U25 U24 V24 T26 U26 V26 W26"),
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("pmod1", "U23 V23 U22 V21 W25 W24 W23 W22"),
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("pmod2", "J24 H22 E21 D18 K22 J21 H21 D22"),
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("pmod3", "E4 F4 E6 H4 F3 D4 D5 F5"),
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("pmod4", "E26 D25 F26 F25 C26 C25 A25 A24"),
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("pmod5", "D19 C21 B21 C22 D21 A21 A22 A23"),
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("pmod6", "C16 B17 C18 B19 A17 A18 A19 C19"),
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("pmod7", "D14 B14 E14 B16 C14 A14 A15 A16"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="85F", toolchain="trellis", **kwargs):
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assert device in ["45F", "85F"]
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LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG554I", _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenFPGALoader("ecpix5")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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