litex-boards/litex_boards/community/targets/de10lite.py

148 lines
5.3 KiB
Python
Executable File

#!/usr/bin/env python3
# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# License: BSD
import argparse
from migen import *
from litex_boards.platforms import de10lite
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc_core import mem_decoder
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
# # #
# main input clock for PLL
clk50 = platform.request("clk50")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(clk50),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk / vga_clk from PLL
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000",
p_CLK2_DIVIDE_BY = 2,
p_CLK2_DUTY_CYCLE = 50,
p_CLK2_MULTIPLY_BY = 1,
p_CLK2_PHASE_SHIFT = "0",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_INTENDED_DEVICE_FAMILY = "MAX 10",
p_LPM_TYPE = "altpll",
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = pll_clk_out,
i_ARESET = ~rst_n,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
self.cd_vga.clk.eq(pll_clk_out[2])
]
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de10lite.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
# VGASoC -------------------------------------------------------------------------------------------
class VGASoC(BaseSoC):
mem_map = {
"terminal": 0x30000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# create VGA terminal
self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(mem_decoder(self.mem_map["terminal"]), self.terminal.bus)
self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
# connect VGA pins
vga = self.platform.request('vga_out', 0)
self.comb += [
vga.vsync_n.eq(terminal.vsync),
vga.hsync_n.eq(terminal.hsync),
vga.r.eq(terminal.red[4:8]),
vga.g.eq(terminal.green[4:8]),
vga.b.eq(terminal.blue[4:8])
]
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-vga", action="store_true", help="enable VGA support")
args = parser.parse_args()
cls = VGASoC if args.with_vga else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()