129 lines
4.3 KiB
Python
129 lines
4.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("M15"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("G14"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D18"), IOStandard("LVCMOS33")),
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# Switches
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("user_sw", 0, Pins("G15"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("P15"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("W13"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("T16"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("V16"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("T17")),
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Subsignal("rx", Pins("Y17")),
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IOStandard("LVCMOS33")
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),
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]
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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_usb_uart_pmod_io = [
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# USB-UART PMOD on JB:
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# - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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("usb_uart", 0,
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Subsignal("tx", Pins("pmodb:1")),
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Subsignal("rx", Pins("pmodb:2")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
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("pmodb", "V8 W8 U7 V7 Y7 Y6 V6 W6"),
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("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
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("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
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("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
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]
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ps7_config = {
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"z7-20" : {
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"PCW_UIPARAM_DDR_PARTNO" : "MT41K256M16 RE-125",
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"PCW_FPGA_FCLK0_ENABLE" : "1",
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"PCW_UART1_BAUD_RATE" : "115200",
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"PCW_EN_UART1" : "1",
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"PCW_UART1_PERIPHERAL_ENABLE" : "1",
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"PCW_UART1_UART1_IO" : "MIO 48 .. 49",
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"PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V",
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"PCW_USE_M_AXI_GP0" : "1",
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"PCW_USE_S_AXI_GP0" : "1",
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"PCW_USB0_PERIPHERAL_ENABLE" : "1",
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"PCW_USB0_USB0_IO" : "MIO 28 .. 39",
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"PCW_USB0_RESET_ENABLE" : "1",
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"PCW_USB0_RESET_IO" : "MIO 46",
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"PCW_EN_USB0" : "1"
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}
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}
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, variant="z7-20", toolchain="vivado"):
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device = {
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"z7-10": "xc7z010-clg400-1",
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"z7-20": "xc7z020-clg400-1"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.add_extension(_ps7_io)
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self.add_extension(_usb_uart_pmod_io)
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self.ps7_config = ps7_config[variant]
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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