82 lines
3.2 KiB
Python
Executable File
82 lines
3.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.io import CRG
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from litex_boards.platforms import tinyfpga_bx
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from litex.build.lattice.icestorm import icestorm_args, icestorm_argdict
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), with_led_chaser=True, **kwargs):
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platform = tinyfpga_bx.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("clk16"))
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM since too large for iCE40.
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on TinyFPGA BX", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import AT25SF081
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=AT25SF081(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on TinyFPGA BX")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI Flash.")
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target_group.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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icestorm_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build(**icestorm_argdict(args))
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if __name__ == "__main__":
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main()
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