173 lines
7.2 KiB
Python
Executable File
173 lines
7.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Gillham <gillham@roadsign.com>
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store"
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# https://www.aliexpress.com/item/1005001631827738.html
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import os
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from migen import *
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from litex_boards.platforms import hpcstore_xc7k420t
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.phy import s7ddrphy
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from litedram.common import PHYPadsReducer
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from litedram.modules import K4B1G0446F
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst_n = platform.request("cpu_reset_n")
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=120)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6),
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io_voltage="3.3V",
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with_led_chaser = True,
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with_pcie = False,
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with_sata = False,
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**kwargs):
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platform = hpcstore_xc7k420t.Platform(io_voltage)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on HPC Store XC7K420T", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1, 2, 3]),
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#pads = platform.request("ddram", 0),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = K4B1G0446F(sys_clk_freq, "1:4", "800"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# TODO verify / test
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# RefClk, Generate 150MHz from PLL.
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self.clock_domains.cd_sata_refclk = ClockDomain()
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self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
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sata_refclk = ClockSignal("sata_refclk")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
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# PHY
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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refclk = sata_refclk,
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pads = platform.request("sata", 0),
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gen = "gen2",
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# I2C --------------------------------------------------------------------------------------
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self.submodules.i2c = I2CMaster(platform.request("i2c"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress HPC Store XC7K420T")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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target_group.add_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'")
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target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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io_voltage = args.io_voltage,
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with_pcie = args.with_pcie,
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with_sata = args.with_sata,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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