208 lines
9.3 KiB
Python
Executable File
208 lines
9.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
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# litex_server --udp
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# litex_term crossover
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import butterstick
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOTristate
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from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk30 = platform.request("clk30")
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rst_n = platform.request("user_btn", 0)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk30)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk30, 30e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI = self.cd_sys2x_i.clk,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6),
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toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
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eth_dynamic_ip = False,
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with_spi_flash = False,
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with_led_chaser = True,
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with_syzygy_gpio = True,
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**kwargs) :
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platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ButterStick", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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"MT41K64M16": MT41K64M16,
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"MT41K128M16": MT41K128M16,
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"MT41K256M16": MT41K256M16,
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"MT41K512M16": MT41K512M16,
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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rx_delay = 0e-9, # KSZ9031RNX phy adds a 1.2ns RX delay
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.comb += platform.request("user_led_color").eq(0b010) # Blue.
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# GPIOs ------------------------------------------------------------------------------------
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if with_syzygy_gpio:
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platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0"))
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self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
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target_group.add_argument("--device", default="85F", help="ECP5 device (25F, 45F, 85F).")
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target_group.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
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target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sdram_device = args.sdram_device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_spi_flash = args.with_spi_flash,
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with_syzygy_gpio = args.with_syzygy_gpio,
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**soc_core_argdict(args))
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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