251 lines
11 KiB
Python
Executable File
251 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import axi
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from liteeth.phy.trionrgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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clk40 = platform.request("clk40")
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rst_n = platform.request("user_btn", 0)
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# PLL
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self.submodules.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk40, 40e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk")
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6),
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with_spi_flash = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_phy = 0,
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eth_ip = "192.168.1.50",
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with_led_chaser = True,
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**kwargs):
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platform = efinix_trion_t120_bga576_dev_kit.Platform()
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# USBUART PMOD as Serial--------------------------------------------------------------------
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platform.add_extension(efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e"))
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kwargs["uart_name"] = "usb_uart"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
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ident_version = True,
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**kwargs
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
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platform.toolchain.excluded_ios.append(platform.lookup_request("spiflash4x").dq)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Tristate Test ----------------------------------------------------------------------------
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from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
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from litex.soc.cores.bitbang import I2CMaster
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platform.add_extension([("i2c", 0,
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Subsignal("sda", Pins("T12")),
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Subsignal("scl", Pins("V11")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS"),
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)])
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self.submodules.i2c = I2CMaster(pads=platform.request("i2c"))
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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platform = platform,
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clock_pads = platform.request("eth_clocks", eth_phy),
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pads = platform.request("eth", eth_phy),
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with_hw_init_reset = False)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, software_debug=True)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# FIXME: Avoid this.
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").tx)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").rx)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_data)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").rx_data)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio)
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# LPDDR3 SDRAM -----------------------------------------------------------------------------
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if False:
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# DRAM / PLL Blocks.
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# ------------------
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dram_clk = platform.request("br0_pll_clkin")
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platform.toolchain.excluded_ios.append(dram_clk)
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block = {"type" : "DRAM"}
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platform.toolchain.ifacewriter.xml_blocks.append(block)
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block = {"type" : "PLL_DRAM"}
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platform.toolchain.ifacewriter.blocks.append(block)
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# DRAM Rst.
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# ---------
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br0_pll_rstn = platform.add_iface_io("br0_pll_rstn")
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self.comb += br0_pll_rstn.eq(platform.request("user_btn", 1))
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self.specials += Instance("ddr_reset_sequencer",
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i_ddr_rstn_i = ~ResetSignal("sys"),
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i_clk = ClockSignal("sys"),
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o_ddr_rstn = platform.add_iface_io("ddr_inst1_RSTN"),
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o_ddr_cfg_seq_rst = platform.add_iface_io("ddr_inst1_CFG_SEQ_RST"),
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o_ddr_cfg_seq_start = platform.add_iface_io("ddr_inst1_CFG_SEQ_START"),
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o_ddr_init_done = Signal(),
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)
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platform.add_source("ddr_reset_sequencer.v") # FIXME: From example design.
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# DRAM AXI-Port.
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# --------------
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axi_port = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
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ios = [("axi0", 0,
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Subsignal("wdata", Pins(256)),
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Subsignal("wready", Pins(1)),
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Subsignal("wid", Pins(8)),
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Subsignal("bready", Pins(1)),
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Subsignal("rdata", Pins(256)),
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Subsignal("aid", Pins(8)),
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Subsignal("bvalid", Pins(1)),
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Subsignal("rlast", Pins(1)),
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Subsignal("bid", Pins(8)),
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Subsignal("asize", Pins(3)),
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Subsignal("atype", Pins(1)),
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Subsignal("aburst", Pins(2)),
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Subsignal("wvalid", Pins(1)),
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Subsignal("aaddr", Pins(32)),
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Subsignal("rid", Pins(8)),
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Subsignal("avalid", Pins(1)),
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Subsignal("rvalid", Pins(1)),
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Subsignal("alock", Pins(2)),
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Subsignal("rready", Pins(1)),
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Subsignal("rresp", Pins(2)),
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Subsignal("wstrb", Pins(32)),
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Subsignal("aready", Pins(1)),
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Subsignal("alen", Pins(8)),
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Subsignal("wlast", Pins(1)),
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)]
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io = platform.add_iface_ios(ios)
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rw_n = Signal()
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self.comb += rw_n.eq(axi_port.ar.valid)
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self.comb += [
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# Pseudo AW/AR Channels.
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io.atype.eq(~rw_n),
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io.aaddr.eq( Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
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io.aid.eq( Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
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io.alen.eq( Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
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io.asize.eq( Mux(rw_n, axi_port.ar.size[0:4], axi_port.aw.size[0:4])), # CHECKME.
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io.aburst.eq( Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
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io.alock.eq( Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
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io.avalid.eq( Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
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axi_port.aw.ready.eq(~rw_n & io.aready),
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axi_port.ar.ready.eq( rw_n & io.aready),
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# R Channel.
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axi_port.r.id.eq(io.rid),
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axi_port.r.data.eq(io.rdata),
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axi_port.r.last.eq(io.rlast),
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axi_port.r.resp.eq(io.rresp),
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axi_port.r.valid.eq(io.rvalid),
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io.rready.eq(axi_port.r.ready),
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# W Channel.
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io.wid.eq(axi_port.w.id),
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io.wstrb.eq(axi_port.w.strb),
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io.wdata.eq(axi_port.w.data),
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io.wlast.eq(axi_port.w.last),
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io.wvalid.eq(axi_port.w.valid),
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axi_port.w.ready.eq(io.wready),
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# B Channel.
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axi_port.b.id.eq(io.bid),
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axi_port.b.valid.eq(io.bvalid),
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io.bready.eq(axi_port.b.ready),
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]
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# Connect AXI interface to the main bus of the SoC.
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axi_lite_port = axi.AXILiteInterface(data_width=256, address_width=32)
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self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
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self.bus.add_slave("main_ram", axi_lite_port, SoCRegion(origin=0x4000_0000, size=0x1000_0000)) # 256MB.
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_spi_flash = args.with_spi_flash,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_phy = args.eth_phy,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, f"{soc.build_name}.bit"))
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if args.flash:
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from litex.build.openfpgaloader import OpenFPGALoader
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prog = OpenFPGALoader("trion_t120_bga576")
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prog.flash(0, os.path.join(builder.gateware_dir, f"{soc.build_name}.hex"))
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if __name__ == "__main__":
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main()
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