126 lines
5.1 KiB
Python
Executable File
126 lines
5.1 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
from migen import *
|
|
|
|
from litex.gen import LiteXModule
|
|
|
|
from litex_boards.platforms import alchitry_au
|
|
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
|
|
|
|
from litex.soc.interconnect.csr import *
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
from litedram.modules import AS4C128M16
|
|
from litedram.phy import s7ddrphy
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class CRG(LiteXModule):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.rst = Signal()
|
|
self.cd_sys = ClockDomain()
|
|
self.cd_sys4x = ClockDomain()
|
|
self.cd_sys4x_dqs = ClockDomain()
|
|
self.cd_idelay = ClockDomain()
|
|
|
|
# Clk/Rst
|
|
clk100 = platform.request("clk100")
|
|
|
|
# PLL
|
|
self.pll = pll = S7PLL()
|
|
self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
|
|
pll.register_clkin(clk100, 100e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
|
|
pll.create_clkout(self.cd_idelay, 200e6)
|
|
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
|
|
|
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
|
|
|
|
# BaseSoC -----------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, variant="au", sys_clk_freq=int(83333333), with_spi_flash=False, with_led_chaser=True, **kwargs):
|
|
platform = alchitry_au.Platform(variant=variant)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.crg = CRG(platform, sys_clk_freq)
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alchitry Au(+)", **kwargs)
|
|
|
|
# DDR3 SDRAM -------------------------------------------------------------------------------
|
|
if not self.integrated_main_ram_size:
|
|
self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
|
memtype = "DDR3",
|
|
nphases = 4,
|
|
sys_clk_freq = sys_clk_freq,
|
|
iodelay_clk_freq = 200e6)
|
|
self.add_sdram("sdram",
|
|
phy = self.ddrphy,
|
|
module = AS4C128M16(sys_clk_freq, "1:4"),
|
|
l2_cache_size = kwargs.get("l2_size", 8192)
|
|
)
|
|
|
|
# SPI Flash --------------------------------------------------------------------------------
|
|
if with_spi_flash:
|
|
from litespi.modules import SST26VF032B
|
|
from litespi.opcodes import SpiNorFlashOpCodes as Codes
|
|
self.add_spi_flash(mode="4x", module=SST26VF032B(Codes.READ_1_1_1), with_master=True)
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
from litex.soc.integration.soc import LiteXSoCArgumentParser
|
|
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Au(+)")
|
|
target_group = parser.add_argument_group(title="Target options")
|
|
target_group.add_argument("--build", action="store_true", help="Build design.")
|
|
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
|
|
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
|
|
target_group.add_argument("--variant", default="au", help="Board variant (au or au+).")
|
|
target_group.add_argument("--sys-clk-freq", default=83333333, help="System clock frequency.")
|
|
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
|
|
builder_args(parser)
|
|
soc_core_args(parser)
|
|
vivado_build_args(parser)
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(
|
|
variant = args.variant,
|
|
sys_clk_freq = int(float(args.sys_clk_freq)),
|
|
with_spi_flash = args.with_spi_flash,
|
|
**soc_core_argdict(args)
|
|
)
|
|
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
if args.build:
|
|
builder.build(**vivado_build_argdict(args))
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
|
|
|
if args.flash:
|
|
prog = soc.platform.create_programmer()
|
|
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
|
|
|
|
if __name__ == "__main__":
|
|
main()
|