106 lines
3.7 KiB
Python
Executable File
106 lines
3.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 JM Robles <roblesjm@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import LiteXModule
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from litex_boards.platforms import fpgawars_alhambra2
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from litex.build.lattice.programmer import IceStormProgrammer
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from litex.build.lattice.icestorm import icestorm_args, icestorm_argdict
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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assert sys_clk_freq == 12e6
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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sys = platform.request("clk12")
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platform.add_period_constraint(sys, 1e9/12e6)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal("sys"))
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count -1))
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# Sys clk
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self.comb += self.cd_sys.clk.eq(sys)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done)
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(12e6), with_led_chaser=True, bios_flash_offset=0x50000, **kwargs):
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platform = fpgawars_alhambra2.Platform()
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kwargs["integrated_rom_size"] = 0
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# SoC
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SoCCore.__init__(self, platform, sys_clk_freq, ident='Litex on Alhambra II', **kwargs)
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# SPI Flash
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from litespi.modules import N25Q032A
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode='1x', module=N25Q032A(Codes.READ_1_1_1), with_master=False)
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self.bus.add_region("rom", SoCRegion(
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origin=self.bus.regions["spiflash"].origin + bios_flash_offset,
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size=32*kB,
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linker=True
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))
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# CRG
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self.crg = _CRG(platform, sys_clk_freq)
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# Leds
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if with_led_chaser:
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self.leds = LedChaser(pads=platform.request_all("user_leds"), sys_clk_freq=sys_clk_freq)
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
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target_group.add_argument("--toolchain", default="icestorm", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI flash")
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target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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builder_args(parser)
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soc_core_args(parser)
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icestorm_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build(**icestorm_argdict(args))
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if args.flash:
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flash(args.bios_flash_offset)
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if __name__ == "__main__":
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main()
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