265 lines
11 KiB
Python
Executable File
265 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import LiteXModule
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from litex.soc.cores.clock.gowin_gw2a import GW2APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser, WS2812
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.video import *
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from liteeth.phy.rmii import LiteEthPHYRMII
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from litex_boards.platforms import sipeed_tang_primer_20k
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from litedram.common import PHYPadsReducer
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from litedram.modules import MT41J128M16
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from litedram.phy import GW2DDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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self.cd_init = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk
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clk27 = platform.request("clk27")
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# Power on reset (the onboard POR is not aware of reprogramming)
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk27)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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self.specials += [
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Instance("DHCEN",
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i_CLKIN = self.cd_sys2x_i.clk,
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i_CE = self.stop,
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o_CLKOUT = self.cd_sys2x.clk),
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Instance("CLKDIV",
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p_DIV_MODE = "2",
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i_CALIB = 0,
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i_HCLKIN = self.cd_sys2x.clk,
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i_RESETN = ~self.reset,
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o_CLKOUT = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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]
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# Init clock domain
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self.comb += self.cd_init.clk.eq(clk27)
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self.comb += self.cd_init.rst.eq(pll.reset)
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# Video PLL
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if with_video_pll:
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self.video_pll = video_pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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video_pll.register_clkin(clk27, 27e6)
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=1e-3)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE = "5",
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i_RESETN = 1, # Disable reset signal.
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i_CALIB = 0, # No calibration.
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i_HCLKIN = self.cd_hdmi5x.clk,
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(48e6),
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with_spi_flash = False,
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with_led_chaser = True,
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with_rgb_led = False,
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with_buttons = True,
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with_video_terminal = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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dock = "standard",
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**kwargs):
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assert dock in ["standard", "lite"]
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platform = sipeed_tang_primer_20k.Platform(dock, toolchain="gowin")
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if dock == "lite":
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with_led_chaser = False # No leds on core board nor on dock lite.
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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# FIXME: WIP.
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if not self.integrated_main_ram_size:
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self.ddrphy = GW2DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
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sys_clk_freq = sys_clk_freq
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)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:2"),
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l2_cache_size = 0
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)
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# ./sipeed_tang_primer_20k.py --cpu-variant=lite --uart-name=crossover+uartbone --csr-csv=csr.csv --build --load
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# litex_server --uart --uart-port=/dev/ttyUSB2
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# litex_term crossover
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# litescope_cli
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if kwargs["uart_name"] == "crossover+uartbone":
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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self.ddrphy.dfi.p0,
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self.ddrphy.dfi.p0.wrdata_en,
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self.ddrphy.dfi.p1.rddata_en,
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]
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self.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 128,
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clock_domain = "sys",
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q32JV as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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# FIXME: Un-tested.
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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refclk_cd = None
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, with_timing_constraints=False)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_timing_constraints=False)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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# FIXME: Un-tested.
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hdmi_pads = platform.request("hdmi")
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self.comb += hdmi_pads.hdp.eq(1)
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self.videophy = VideoHDMIPHY(hdmi_pads, clock_domain="hdmi", pn_swap=["r", "g", "b"])
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led"),
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sys_clk_freq = sys_clk_freq
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)
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# RGB Led ----------------------------------------------------------------------------------
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if with_rgb_led:
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self.rgb_led = WS2812(
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pad = platform.request("rgb_led"),
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nleds = 1,
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sys_clk_freq = sys_clk_freq
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)
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self.bus.add_slave(name="rgb_led", slave=self.rgb_led.bus, region=SoCRegion(
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origin = 0x2000_0000,
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size = 4,
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))
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn_n"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Primer 20K")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--dock", default="standard", help="Dock version (standard (default) or lite.")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
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target_group.add_argument("--eth-ip", default="192.168.1.50", help="Etherbone IP address.")
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target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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dock = args.dock,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"), external=True)
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if __name__ == "__main__":
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main()
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