180 lines
7.1 KiB
Python
Executable File
180 lines
7.1 KiB
Python
Executable File
#!/usr/bin/env python3
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'''
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---------------------
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LiteX SoC on Marble
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---------------------
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with support for SO-DIMM DDR3, ethernet and UART.
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To synthesize, add --build, to configure the FPGA over jtag, add --load.
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-----------------
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Example configs
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-----------------
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with ethernet and DDR3, default IP: 192.168.1.50/24
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./marble.py --with-ethernet --with-bist --spd-dump VR7PU286458FBAMJT.txt
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lightweight config
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./marble.py --integrated-main-ram-size 16384 --cpu-type serv
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etherbone: access wishbone over ethernet
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./marble.py --with-etherbone --csr-csv build/csr.csv
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make sure reset is not asserted (RTS signal), set PC IP to 192.168.1.100/24,
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then test and benchmark the etherbone link:
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cd build
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litex/liteeth/bench/test_etherbone.py --udp --ident --access --sram --speed
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'''
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from migen import *
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from litex_boards.platforms import berkeleylab_marble
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import MT8JTF12864, parse_spd_hexdump, SDRAMModule
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, resets=[]):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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resets.append(self.rst)
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self.comb += pll.reset.eq(reduce(or_, resets))
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6),
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with_ethernet = False,
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with_etherbone = False,
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with_rts_reset = False,
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with_led_chaser = True,
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spd_dump = None,
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**kwargs
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):
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platform = berkeleylab_marble.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Berkeley-Lab Marble",
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**kwargs)
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# CRG, resettable over USB serial RTS signal -----------------------------------------------
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resets = []
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if with_rts_reset:
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ser_pads = platform.lookup_request('serial')
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resets.append(ser_pads.rts)
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self.submodules.crg = _CRG(platform, sys_clk_freq, resets)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
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platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq
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)
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if spd_dump is not None:
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ram_spd = parse_spd_hexdump(spd_dump)
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ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq)
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print('DDR3: loaded config from', spd_dump)
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else:
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ram_module = MT8JTF12864(sys_clk_freq, "1:4") # KC705 chip, 1 GB
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print('DDR3: No spd data specified, falling back to MT8JTF12864')
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self.add_sdram(
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"sdram",
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phy = self.ddrphy,
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module = ram_module,
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# size=0x40000000, # Limit its size to 1 GB
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l2_cache_size = kwargs.get("l2_size", 8192),
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with_bist = kwargs.get("with_bist", False)
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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tx_delay=0
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)
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if with_ethernet:
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self.add_ethernet(
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phy=self.ethphy,
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dynamic_ip=True,
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software_debug=False
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)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# System I2C (behing multiplexer) ----------------------------------------------------------
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i2c_pads = platform.request('i2c_fpga')
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self.submodules.i2c = I2CMaster(i2c_pads)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on BerkeleyLab Marble")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset.")
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parser.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker.")
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parser.add_argument("--spd-dump", type=str, help="DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_bist = args.with_bist,
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spd_dump = args.spd_dump,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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