Sylvain Munaut dc92584681 adi_adrv2crr: Upgrade part to speedgrade 2 ... Even though the schematic and bom call for speedgrade 1, this was only for the prototypes. All productions units have been updated to speedgrade 2. See this thread: https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade And the official HDL project for the board: https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2022-03-22 23:36:41 +01:00
..
platforms	adi_adrv2crr: Upgrade part to speedgrade 2	2022-03-22 23:36:41 +01:00
prog	add openocd config for litex acorn baseboard	2022-02-13 16:44:40 +01:00
targets	targets: Remove l2_size workaround (no longer required).	2022-03-22 19:13:23 +01:00
__init__.py	alinx_axu2gca: new board	2022-01-25 07:35:42 +01:00