526 lines
18 KiB
Python
526 lines
18 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
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("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
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("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
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("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
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("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
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("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
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("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
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("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
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("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
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("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
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("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
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("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
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("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
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("user_sma_clock", 0,
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Subsignal("p", Pins("D23"), IOStandard("LVDS")),
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Subsignal("n", Pins("C23"), IOStandard("LVDS"))
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),
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("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
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("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
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("user_sma_gpio", 0,
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Subsignal("p", Pins("H27"), IOStandard("LVDS")),
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Subsignal("n", Pins("G27"), IOStandard("LVDS"))
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),
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("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")),
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("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")),
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("clk125", 0,
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Subsignal("p", Pins("G10"), IOStandard("LVDS")),
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Subsignal("n", Pins("F10"), IOStandard("LVDS"))
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),
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("clk300", 0,
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Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
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Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
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),
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("i2c", 0,
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Subsignal("scl", Pins("J24")),
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Subsignal("sda", Pins("J25")),
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IOStandard("LVCMOS18")
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),
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("serial", 0,
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Subsignal("cts", Pins("L23")),
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Subsignal("rts", Pins("K27")),
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Subsignal("tx", Pins("K26")),
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Subsignal("rx", Pins("G25")),
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IOStandard("LVCMOS18")
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),
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("spiflash", 0, # clock needs to be accessed through primitive
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Subsignal("cs_n", Pins("U7")),
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Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
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IOStandard("LVCMOS18")
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),
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("spiflash", 1, # clock needs to be accessed through primitive
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Subsignal("cs_n", Pins("G26")),
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Subsignal("dq", Pins("M20 L20 R21 R22")),
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IOStandard("LVCMOS18")
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),
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("sdcard", 0,
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Subsignal("clk", Pins("AL10")),
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Subsignal("cmd", Pins("AD9"), Misc("PULLUP True")),
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Subsignal("data", Pins("AP9 AN9 AH9 AH8"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18")
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),
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("spisdcard", 0,
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Subsignal("clk", Pins("AL10")),
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Subsignal("cs_n", Pins("AH8")),
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Subsignal("mosi", Pins("AD9"), Misc("PULLUP")),
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Subsignal("miso", Pins("AP9"), Misc("PULLUP")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18")
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),
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("rotary", 0,
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Subsignal("a", Pins("Y21")),
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Subsignal("b", Pins("AD26")),
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Subsignal("push", Pins("AF28")),
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IOStandard("LVCMOS18")
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),
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("hdmi", 0,
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Subsignal("d", Pins(
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"AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
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"AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
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"AG10 AK8")),
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Subsignal("de", Pins("AE11")),
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Subsignal("clk", Pins("AF13")),
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Subsignal("vsync", Pins("AH13")),
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Subsignal("hsync", Pins("AE13")),
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Subsignal("spdif", Pins("AE12")),
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Subsignal("spdif_out", Pins("AF12")),
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IOStandard("LVCMOS18")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
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"AF18 AH19 AF15 AD19 AJ14 AG19"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
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#Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
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"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
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"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
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"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
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"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
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"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
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"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
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"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2")),
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Subsignal("rx_n", Pins("AB1")),
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Subsignal("tx_p", Pins("AC4")),
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Subsignal("tx_n", Pins("AC3"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2")),
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Subsignal("rx_n", Pins("AB1 AD1")),
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Subsignal("tx_p", Pins("AC4 AE4")),
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Subsignal("tx_n", Pins("AC3 AE3"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
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Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
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Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")),
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Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5"))
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),
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("pcie_x8", 0,
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Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
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Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
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Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
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Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
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),
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("sgmii_clock", 0,
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Subsignal("p", Pins("P26"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("N26"), IOStandard("LVDS_25"))
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),
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("si570_refclk", 0,
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Subsignal("p", Pins("P6")),
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Subsignal("n", Pins("P5"))
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),
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("user_sma_mgt_refclk", 0,
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Subsignal("p", Pins("V6")),
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Subsignal("n", Pins("V5"))
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),
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("user_sma_mgt_tx", 0,
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Subsignal("p", Pins("R4")),
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Subsignal("n", Pins("R3"))
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),
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("user_sma_mgt_rx", 0,
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Subsignal("p", Pins("P2")),
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Subsignal("n", Pins("P1"))
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),
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("sfp", 0,
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Subsignal("txp", Pins("U4")),
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Subsignal("txn", Pins("U3")),
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Subsignal("rxp", Pins("T2")),
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Subsignal("rxn", Pins("T1"))
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),
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("sfp_tx", 0,
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Subsignal("p", Pins("U4")),
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Subsignal("n", Pins("U3")),
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("T2")),
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Subsignal("n", Pins("T1")),
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),
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("sfp_tx_disable_n", 0, Pins("AL8"), IOStandard("LVCMOS18")),
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("sfp", 1,
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Subsignal("txp", Pins("W4")),
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Subsignal("txn", Pins("W3")),
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Subsignal("rxp", Pins("V2")),
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Subsignal("rxn", Pins("V1"))
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),
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("sfp_tx", 1,
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Subsignal("p", Pins("W4")),
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Subsignal("n", Pins("W3")),
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),
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("sfp_rx", 1,
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Subsignal("p", Pins("V2")),
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Subsignal("n", Pins("V1")),
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),
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("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("HPC", {
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"DP0_C2M_P" : "F6",
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"DP0_C2M_N" : "F5",
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"DP0_M2C_P" : "E4",
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"DP0_M2C_N" : "E3",
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"DP1_C2M_P" : "D6",
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"DP1_C2M_N" : "D5",
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"DP1_M2C_P" : "D2",
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"DP1_M2C_N" : "D1",
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"DP2_C2M_P" : "C4",
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"DP2_C2M_N" : "C3",
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"DP2_M2C_P" : "B2",
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"DP2_M2C_N" : "B1",
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"DP3_C2M_P" : "B6",
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"DP3_C2M_N" : "B5",
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"DP3_M2C_P" : "A4",
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"DP3_M2C_N" : "A3",
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"DP4_C2M_P" : "N4",
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"DP4_C2M_N" : "N3",
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"DP4_M2C_P" : "M2",
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"DP4_M2C_N" : "M1",
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"DP5_C2M_P" : "J4",
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"DP5_C2M_N" : "J3",
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"DP5_M2C_P" : "H2",
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"DP5_M2C_N" : "H1",
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"DP6_C2M_P" : "L4",
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"DP6_C2M_N" : "L3",
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"DP6_M2C_P" : "K2",
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"DP6_M2C_N" : "K1",
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"DP7_C2M_P" : "G4",
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"DP7_C2M_N" : "G3",
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"DP7_M2C_P" : "F2",
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"DP7_M2C_N" : "F1",
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"LA06_P" : "D13",
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"LA06_N" : "C13",
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"LA10_P" : "L8",
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"LA10_N" : "K8",
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"LA14_P" : "B10",
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"LA14_N" : "A10",
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"LA18_CC_P" : "E22",
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"LA18_CC_N" : "E23",
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"LA27_P" : "H21",
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"LA27_N" : "G21",
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"HA01_CC_P" : "E16",
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"HA01_CC_N" : "D16",
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"HA05_P" : "J15",
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"HA05_N" : "J14",
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"HA09_P" : "F18",
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"HA09_N" : "F17",
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"HA13_P" : "B14",
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"HA13_N" : "A14",
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"HA16_P" : "A19",
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"HA16_N" : "A18",
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"HA20_P" : "C19",
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"HA20_N" : "B19",
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"CLK1_M2C_P" : "E25",
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"CLK1_M2C_N" : "D25",
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"LA00_CC_P" : "H11",
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"LA00_CC_N" : "G11",
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"LA03_P" : "A13",
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"LA03_N" : "A12",
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"LA08_P" : "J8",
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"LA08_N" : "H8",
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"LA12_P" : "E10",
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"LA12_N" : "D10",
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"LA16_P" : "B9",
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"LA16_N" : "A9",
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"LA20_P" : "B24",
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"LA20_N" : "A24",
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"LA22_P" : "G24",
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"LA22_N" : "F25",
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"LA25_P" : "D20",
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"LA25_N" : "D21",
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"LA29_P" : "B20",
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"LA29_N" : "A20",
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"LA31_P" : "B25",
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"LA31_N" : "A25",
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"LA33_P" : "A27",
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"LA33_N" : "A28",
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"HA03_P" : "G15",
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"HA03_N" : "G14",
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"HA07_P" : "L19",
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"HA07_N" : "L18",
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"HA11_P" : "J19",
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"HA11_N" : "J18",
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"HA14_P" : "F15",
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"HA14_N" : "F14",
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"HA18_P" : "B17",
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"HA18_N" : "B16",
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"HA22_P" : "C18",
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"HA22_N" : "C17",
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"GBTCLK1_M2C_P" : "H6",
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"GBTCLK1_M2C_N" : "H5",
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"GBTCLK0_M2C_P" : "K6",
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"GBTCLK0_M2C_N" : "K5",
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"LA01_CC_P" : "G9",
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"LA01_CC_N" : "F9",
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"LA05_P" : "L13",
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"LA05_N" : "K13",
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"LA09_P" : "J9",
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"LA09_N" : "H9",
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"LA13_P" : "D9",
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"LA13_N" : "C9",
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"LA17_CC_P" : "D24",
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"LA17_CC_N" : "C24",
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"LA23_P" : "G22",
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"LA23_N" : "F22",
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"LA26_P" : "G20",
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"LA26_N" : "F20",
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"PG_M2C" : "L27",
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"HA00_CC_P" : "G17",
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"HA00_CC_N" : "G16",
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"HA04_P" : "G19",
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"HA04_N" : "F19",
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"HA08_P" : "K18",
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"HA08_N" : "K17",
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"HA12_P" : "K16",
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"HA12_N" : "J16",
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"HA15_P" : "D14",
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"HA15_N" : "C14",
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"HA19_P" : "D19",
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"HA19_N" : "D18",
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"PRSNT_M2C_B" : "H24",
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"CLK0_M2C_P" : "H12",
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"CLK0_M2C_N" : "G12",
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"LA02_P" : "K10",
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"LA02_N" : "J10",
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"LA04_P" : "L12",
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"LA04_N" : "K12",
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"LA07_P" : "F8",
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"LA07_N" : "E8",
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"LA11_P" : "K11",
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"LA11_N" : "J11",
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"LA15_P" : "D8",
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"LA15_N" : "C8",
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"LA19_P" : "C21",
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"LA19_N" : "C22",
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"LA21_P" : "F23",
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"LA21_N" : "F24",
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"LA24_P" : "E20",
|
|
"LA24_N" : "E21",
|
|
"LA28_P" : "B21",
|
|
"LA28_N" : "B22",
|
|
"LA30_P" : "C26",
|
|
"LA30_N" : "B26",
|
|
"LA32_P" : "E26",
|
|
"LA32_N" : "D26",
|
|
"HA02_P" : "H19",
|
|
"HA02_N" : "H18",
|
|
"HA06_P" : "L15",
|
|
"HA06_N" : "K15",
|
|
"HA10_P" : "H17",
|
|
"HA10_N" : "H16",
|
|
"HA17_CC_P" : "E18",
|
|
"HA17_CC_N" : "E17",
|
|
"HA21_P" : "E15",
|
|
"HA21_N" : "D15",
|
|
"HA23_P" : "B15",
|
|
"HA23_N" : "A15",
|
|
}
|
|
),
|
|
("LPC", {
|
|
"GBTCLK0_M2C_P" : "AA24",
|
|
"GBTCLK0_M2C_N" : "AA25",
|
|
"LA01_CC_P" : "W25",
|
|
"LA01_CC_N" : "Y25",
|
|
"LA05_P" : "V27",
|
|
"LA05_N" : "V28",
|
|
"LA09_P" : "V26",
|
|
"LA09_N" : "W26",
|
|
"LA13_P" : "AA20",
|
|
"LA13_N" : "AB20",
|
|
"LA17_CC_P" : "AA32",
|
|
"LA17_CC_N" : "AB32",
|
|
"LA23_P" : "AD30",
|
|
"LA23_N" : "AD31",
|
|
"LA26_P" : "AF33",
|
|
"LA26_N" : "AG34",
|
|
"CLK0_M2C_P" : "AA24",
|
|
"CLK0_M2C_N" : "AA25",
|
|
"LA02_P" : "AA22",
|
|
"LA02_N" : "AB22",
|
|
"LA04_P" : "U26",
|
|
"LA04_N" : "U27",
|
|
"LA07_P" : "V22",
|
|
"LA07_N" : "V23",
|
|
"LA11_P" : "V21",
|
|
"LA11_N" : "W21",
|
|
"LA15_P" : "AB25",
|
|
"LA15_N" : "AB26",
|
|
"LA19_P" : "AA29",
|
|
"LA19_N" : "AB29",
|
|
"LA21_P" : "AC33",
|
|
"LA21_N" : "AD33",
|
|
"LA24_P" : "AE32",
|
|
"LA24_N" : "AF32",
|
|
"LA28_P" : "V31",
|
|
"LA28_N" : "W31",
|
|
"LA30_P" : "Y31",
|
|
"LA30_N" : "Y32",
|
|
"LA32_P" : "W30",
|
|
"LA32_N" : "Y30",
|
|
"LA06_P" : "V29",
|
|
"LA06_N" : "W29",
|
|
"LA10_P" : "T22",
|
|
"LA10_N" : "T23",
|
|
"LA14_P" : "U21",
|
|
"LA14_N" : "U22",
|
|
"LA18_CC_P" : "AB30",
|
|
"LA18_CC_N" : "AB31",
|
|
"LA27_P" : "AG31",
|
|
"LA27_N" : "AG32",
|
|
"CLK1_M2C_P" : "AC31",
|
|
"CLK1_M2C_N" : "AC32",
|
|
"LA00_CC_P" : "W23",
|
|
"LA00_CC_N" : "W24",
|
|
"LA03_P" : "W28",
|
|
"LA03_N" : "Y28",
|
|
"LA08_P" : "U24",
|
|
"LA08_N" : "U25",
|
|
"LA12_P" : "AC22",
|
|
"LA12_N" : "AC23",
|
|
"LA16_P" : "AB21",
|
|
"LA16_N" : "AC21",
|
|
"LA20_P" : "AA34",
|
|
"LA20_N" : "AB34",
|
|
"LA22_P" : "AC34",
|
|
"LA22_N" : "AD34",
|
|
"LA25_P" : "AE33",
|
|
"LA25_N" : "AF34",
|
|
"LA29_P" : "U34",
|
|
"LA29_N" : "V34",
|
|
"LA31_P" : "V33",
|
|
"LA31_N" : "W34",
|
|
"LA33_P" : "W33",
|
|
"LA33_N" : "Y33",
|
|
}
|
|
)
|
|
]
|
|
|
|
# Platform -----------------------------------------------------------------------------------------
|
|
|
|
class Platform(XilinxPlatform):
|
|
default_clk_name = "clk125"
|
|
default_clk_period = 1e9/125e6
|
|
|
|
def __init__(self):
|
|
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
|
|
|
|
def create_programmer(self):
|
|
return VivadoProgrammer()
|
|
|
|
def do_finalize(self, fragment):
|
|
XilinxPlatform.do_finalize(self, fragment)
|
|
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
|
|
self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
|
|
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
|
|
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
|
|
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
|