85 lines
2.5 KiB
Python
85 lines
2.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Dhiru Kholia <dhiru.kholia@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.xilinx.programmer import XC3SProg
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk33_333", 0, Pins("N18"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("W14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("W13"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("B20")),
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Subsignal("rx", Pins("B19")),
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IOStandard("LVCMOS33")
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),
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]
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# This is currently untested on this EBAZ4205 board
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk33_333"
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default_clk_period = 1e9/33.333e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
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self.add_extension(_ps7_io)
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def create_programmer(self):
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return VivadoProgrammer()
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"""
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# We will like to use this later - Vivado is slow!
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def create_programmer(self):
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return XC3SProg(cable="ftdi")
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"""
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk33_333", loose=True), 1e9/33.333e6)
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