129 lines
4.7 KiB
Python
129 lines
4.7 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk100", 0, Pins("AA10"), IOStandard("LVCMOS15")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("D15")),
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Subsignal("rx", Pins("C18")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("dq", Pins("B24 A25 B22 A22")),
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IOStandard("LVCMOS33")
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),
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# SDCard.
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("spisdcard", 0,
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Subsignal("clk", Pins("C11")),
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Subsignal("mosi", Pins("A15"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins("B15"), Misc("PULLUP True")),
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Subsignal("miso", Pins("A14"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("A14 B10 A12 B15"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("A15"), Misc("PULLUP True")),
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Subsignal("clk", Pins("C11")),
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Subsignal("cd", Pins("A10")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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# RGMII Ethernet
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("eth_refclk", 0, Pins("F17"), IOStandard("LVCMOS33")), # CHECKME: Drive it?
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("eth_clocks", 0,
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Subsignal("tx", Pins("E18")),
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Subsignal("rx", Pins("D18")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("G17"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("E16"), IOStandard("LVCMOS33")),
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Subsignal("mdio", Pins("E15"), IOStandard("LVCMOS33")),
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Subsignal("mdc", Pins("E17"), IOStandard("LVCMOS33")),
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Subsignal("rx_ctl", Pins("F15"), IOStandard("LVCMOS33")),
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Subsignal("rx_data", Pins("J15 J16 F20 D20"), IOStandard("LVCMOS33")),
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Subsignal("tx_ctl", Pins("D19"), IOStandard("LVCMOS33")),
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Subsignal("tx_data", Pins("H18 H17 G19 F18"), IOStandard("LVCMOS33")),
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("G12")),
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Subsignal("sda", Pins("A13")),
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IOStandard("LVCMOS18"),
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),
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"AC8 AA7 AA8 AF7 AE7 AC11 V9 Y10",
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"AB11 Y7 Y8 V11 V8 W11 Y11 V7 "),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AC7 AB7 AB9"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AA9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AD8"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AC9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AD9"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"U6 Y3 AB6 AD4"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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" V4 W3 U5 U1 U7 U2 V6 V3",
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" Y2 Y1 AA3 V2 AC2 W1 AB2 V1",
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"AA4 AB4 AC4 AC3 AC6 Y6 Y5 AD6",
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"AD1 AE1 AE3 AE2 AE6 AE5 AF3 AF2"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("W6 AB1 AA5 AF5"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("W5 AC1 AB5 AF4"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("W10"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("W9"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AB12"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AC12"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AA2"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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