101 lines
3.1 KiB
Python
101 lines
3.1 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Martin Troiber <martin.troiber@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
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# Switches
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("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("T14")), #AR0
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Subsignal("rx", Pins("U12")), #AR1
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IOStandard("LVCMOS33")
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),
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]
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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_usb_uart_pmod_io = [
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# USB-UART PMOD on JB:
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# - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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("usb_uart", 0,
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Subsignal("tx", Pins("pmodb:1")),
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Subsignal("rx", Pins("pmodb:2")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"),
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("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain="vivado")
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self.add_extension(_ps7_io)
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self.add_extension(_usb_uart_pmod_io)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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