118 lines
4.4 KiB
Python
Executable File
118 lines
4.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import orangecrab
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K64M16
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from litedram.phy import ECP5DDRPHY
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# _CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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platform.add_period_constraint(clk48, 1e9/48e6)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout,
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),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.cd_sys2x.rst,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", **kwargs):
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platform = orangecrab.Platform(toolchain=toolchain)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("ECP5DDRPHY", None)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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sdram_module = MT41K64M16(sys_clk_freq, "1:2")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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soc_sdram_args(parser)
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trellis_args(parser)
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args))
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if __name__ == "__main__":
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main()
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