mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
3bb84b0071
Mini Monitor 4K and Mini Recorder 4K are almost the same hardware with just changes on the Video In/Out. For now tests have been done on the Mini Monitor 4K, but the aim is support both boards in the same platform/target in the future, thus the mini_4k naming. These boards could be used as affordable Artix7 dev boards for LiteX, to run Linux with LiteX (512MB of RAM + a Video Framebuffer) or to create custom systems like a fast software defined signal generator/recorder directly from a PC over PCIe, custom HDMI/SDI video cards, etc... lots of possibilities :)
149 lines
5.4 KiB
Python
149 lines
5.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk100", 0, Pins("P16"), IOStandard("LVCMOS25")),
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("clk24", 0, Pins("M21"), IOStandard("LVCMOS25")),
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# Debug
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("debug", 0, Pins("R7"), IOStandard("LVCMOS25")),
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("debug", 1, Pins("R6"), IOStandard("LVCMOS25")),
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("debug", 2, Pins("T7"), IOStandard("LVCMOS25")),
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("debug", 3, Pins("T8"), IOStandard("LVCMOS25")),
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# Fan
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("fan", 0, Pins("R18"), IOStandard("LVCMOS25")),
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# Flash
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("flash_cs_n", 0, Pins("P18"), IOStandard("LVCMOS25")),
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("flash", 0,
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Subsignal("mosi", Pins("R14")),
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Subsignal("miso", Pins("R15")),
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Subsignal("vpp", Pins("P14")),
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Subsignal("hold", Pins("N14")),
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IOStandard("LVCMOS25")
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),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("R7")), # debug0
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Subsignal("rx", Pins("R6")), # debug1
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IOStandard("LVCMOS25")
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),
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# PCIe
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("M19"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F11")),
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Subsignal("clk_n", Pins("E11")),
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Subsignal("rx_p", Pins("B11 D14 B13 D12")),
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Subsignal("rx_n", Pins("A11 C14 A13 C12")),
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Subsignal("tx_p", Pins("B7 D8 B9 D10")),
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Subsignal("tx_n", Pins("A7 C8 A9 C10"))
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"K2 M5 M2 K1 N6 J1 P1 H2",
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"R1 M1 M6 N3 M7 H1"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("K3 N2 L3"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("L7"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("L5"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L2"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("K5"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("G8 J6 D5 A3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G6 H8 F7 F8 D6 H9 E6 H6",
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"J5 G4 L8 F4 K6 G5 K7 K8",
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"A4 D4 B4 E5 C4 F3 C3 D3",
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"G1 D1 G2 A2 E1 E2 F2 C2"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("H7 J4 B5 C1"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("G7 H4 A5 B1"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("P4"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("N4"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("N7"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("J3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N1"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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# SDI
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("sdi_refclk_sel", 0, Pins("AB26"), IOStandard("LVCMOS25")),
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("sdi_refclk", 0,
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Subsignal("p", Pins("AA13")),
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Subsignal("n", Pins("AB13")),
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),
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("sdi_refclk", 1,
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Subsignal("p", Pins("AA11")),
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Subsignal("n", Pins("AB11")),
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),
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("sdi_data", 0,
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Subsignal("txp", Pins("AC10")),
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Subsignal("txn", Pins("AD10")),
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Subsignal("rxp", Pins("AC12")),
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Subsignal("rxn", Pins("AD12")),
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),
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# HDMI (through 75DP159)
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("U14"), IOStandard("LVDS_25")),
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Subsignal("clk_n", Pins("V14"), IOStandard("LVDS_25")),
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Subsignal("data0_p", Pins("AE7")),
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Subsignal("data0_n", Pins("AF7")),
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Subsignal("data1_p", Pins("AC8")),
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Subsignal("data1_n", Pins("AD8")),
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Subsignal("data2_p", Pins("AE9")),
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Subsignal("data2_n", Pins("AD10")),
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# FIXME: Find a way to avoid RX pads.
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Subsignal("rx0_p", Pins("AE11")),
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Subsignal("rx0_n", Pins("AF11")),
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Subsignal("rx1_p", Pins("AC14")),
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Subsignal("rx1_n", Pins("AD14")),
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Subsignal("rx2_p", Pins("AE13")),
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Subsignal("rx2_n", Pins("AF13")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a100t-fgg676-3", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a100t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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from litex.build.xilinx import symbiflow
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
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