238 lines
11 KiB
Python
Executable File
238 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Lukas F. Hartmann, MNT Research GmbH <lukas@mntre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex_boards.platforms import mnt_rkx7
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect.wishbone import *
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.usb_ohci import USBOHCI
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from migen.fhdl.specials import Tristate
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from litedram.modules import IS43TR16512B
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_dvi = ClockDomain(reset_less=True)
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self.clock_domains.cd_usb = ClockDomain()
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clkin = platform.request("clk100")
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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# Main clock input (100MHz)
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pll.register_clkin(clkin, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# USB clock
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pll.create_clkout(self.cd_usb, 48e6)
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self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
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self.comb += pll2.reset.eq(self.rst)
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pll2.register_clkin(clkin, 100e6)
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# DVI/HDMI pixel clock
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pll2.create_clkout(self.cd_dvi, 80e6) # display wants 162e6, but we can underclock
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platform.add_false_path_constraints(self.cd_sys.clk, pll2.clkin)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{
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# FIXME: ends up as 0x7f000000 in linux
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"video_framebuffer": 0x3f000000,
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"usb_ohci": 0xc0000000,
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}}
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=True, with_etherbone=False,
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with_spi_flash=True, with_usb_host=False, **kwargs):
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platform = mnt_rkx7.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MNT-RKX7", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = IS43TR16512B(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192), # TBD: is L2 really necessary?
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), rate="1:1", with_master=True)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{main_ethphy_eth_rx_clk_ibuf}}]")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {{soclinux_ethphy_eth_rx_clk_ibuf}}]")
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True, software_debug=False)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# GPIO -------------------------------------------------------------------------------------
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# Controllable as faux "leds"
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# These are reset pins of various chips
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# We toggle them in LiteX BIOS
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reset_signals = platform.request("resets")
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self.comb += reset_signals.eq(Signal(6, reset=0b111111))
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gpio_signals = platform.request("gpio")
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self.submodules.leds = GPIOOut(gpio_signals)
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self.add_csr("leds")
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# Additional I2C Ports ---------------------------------------------------------------------
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self.submodules.i2c0 = I2CMaster(platform.request("i2c", 0))
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self.submodules.i2c1 = I2CMaster(platform.request("i2c", 1))
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self.submodules.i2c2 = I2CMaster(platform.request("i2c", 2))
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# JTAG -------------------------------------------------------------------------------------
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#self.add_jtagbone()
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# Backlight --------------------------------------------------------------------------------
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# Motherboard display connector backlight, currently unused (the new backlight signals
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# are on the 50pin RGB->eDP connector)
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backlight = platform.request("backlight")
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self.comb += backlight.en.eq(Signal(reset=1))
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self.comb += backlight.pwm.eq(Signal(reset=1))
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# eDP --------------------------------------------------------------------------------------
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video_timings = ("1920x1080@rkx7", {
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"pix_clk" : 162e6,
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"h_active" : 1920,
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"h_blanking" : 159, # off by one in vtg
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"h_sync_offset" : 40,
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"h_sync_width" : 40,
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"v_active" : 1080,
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"v_blanking" : 32,
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"v_sync_offset" : 4,
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"v_sync_width" : 4,
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})
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self.submodules.videophy = VideoDVIPHY(platform.request("edp"), clock_domain="dvi")
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self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
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# HDMI -------------------------------------------------------------------------------------
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# Untested: 2x VideoDVIPHYs and framebuffers in parallel
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#self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="dvi")
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.submodules.usb_ohci = USBOHCI(platform, platform.request("usb"))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# LiteScope UART
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self.add_uartbone(name="litescope_serial")
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# LiteScope Analyzer (optional)
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# analyzer_signals = [
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# ulpi_data.din,
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# utmi.linestate,
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# utmi.txvalid,
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# utmi.rxerror,
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# utmi.rxvalid,
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# usb_ulpi.dir,
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# usb_ulpi.stp,
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# usb_ulpi.nxt,
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# usbh_dbg_state,
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# ulpi_dbg_state,
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# usb_host_intr,
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# usb_host_dbg_intr,
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# ]
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# from litescope import LiteScopeAnalyzer
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# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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# depth = 256,
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# clock_domain = "ulpi",
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# csr_csv = "analyzer.csv")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on MNT-RKX7")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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target_group.add_argument("--with-spi-flash", action="store_true", default=True, help="Enable SPI Flash (MMAPed).")
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target_group.add_argument("--with-usb-host", action="store_true", default=False, help="Enable USB host support.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", default=True, help="Enable SDCard support.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", default=True, help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_spi_flash = args.with_spi_flash,
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with_usb_host = args.with_usb_host,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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args.csr_csv="csr.csv"
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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