100 lines
3.4 KiB
Python
100 lines
3.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.gowin.programmer import GowinProgrammer
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("P16"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("U4"), IOStandard("LVCMOS15")),
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# Serial.
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("serial", 0,
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Subsignal("rx", Pins("N16")),
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Subsignal("tx", Pins("P15")),
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IOStandard("LVCMOS33")
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),
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# Leds
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("led_n", 0, Pins("J14"), IOStandard("LVCMOS33")),
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("led_n", 1, Pins("R26"), IOStandard("LVCMOS33")),
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("led_n", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("led_n", 3, Pins("M25"), IOStandard("LVCMOS33")),
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("led_n", 4, Pins("N21"), IOStandard("LVCMOS33")),
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("led_n", 5, Pins("N23"), IOStandard("LVCMOS33")),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("H24")),
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Subsignal("rx", Pins("C23")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("E17")),
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Subsignal("mdio", Pins("K22")),
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Subsignal("mdc", Pins("K23")),
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Subsignal("rx_ctl", Pins("C22")),
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Subsignal("rx_data", Pins("B26 C26 D26 E26")),
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Subsignal("tx_ctl", Pins("J24")),
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Subsignal("tx_data", Pins("K21 J21 L19 K18")),
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IOStandard("LVCMOS33"),
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),
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("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("sdram_clock", 0, Pins("AC26"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V17 U15 V16 U16 T23 T25 R25 P25",
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"W23 V23 W21 U24 U25")),
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Subsignal("dq", Pins(
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"V22 U22 W19 V19 Y20 W20 V26 U26",
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"AB25 AB26 AA25 AA24 Y26 Y25 W26 W25")),
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Subsignal("ba", Pins("P21 Y21")),
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Subsignal("cas_n", Pins("P24")),
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Subsignal("cs_n", Pins("U14")),
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Subsignal("ras_n", Pins("P23")),
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Subsignal("we_n", Pins("R23")),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# TODO
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, dock="standard", toolchain="gowin"):
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GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B")
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self.toolchain.options["use_sspi_as_gpio"] = 1
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self.toolchain.options["use_cpu_as_gpio"] = 1
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self.toolchain.options["rw_check_on_ram"] = 1
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self.toolchain.options["bit_security"] = 0
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self.toolchain.options["bit_encrypt"] = 0
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self.toolchain.options["bit_compress"] = 0
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def create_programmer(self, kit="openfpgaloader"):
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return OpenFPGALoader(cable="ft2232")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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