112 lines
3.0 KiB
Python
112 lines
3.0 KiB
Python
# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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import subprocess
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import unittest
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import os
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from migen import *
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from litex.soc.integration.builder import *
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RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
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def build_test(socs):
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errors = 0
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for soc in socs:
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os.system("rm -rf build")
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builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
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builder.build()
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errors += not os.path.isfile("./build/gateware/top.v")
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os.system("rm -rf build")
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return errors
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class TestTargets(unittest.TestCase):
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# Build simple design for all platforms
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def test_simple(self):
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platforms = []
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# Xilinx Spartan6
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platforms.append("linsn_rv901t")
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platforms.append("minispartan6")
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platforms.append("pipistrello")
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platforms.append("sp605")
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# Xilinx Artix7
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platforms.append("ac701")
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platforms.append("aller")
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platforms.append("arty")
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platforms.append("mimas_a7")
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platforms.append("netv2")
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platforms.append("nexys4ddr")
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platforms.append("nexys_video")
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platforms.append("tagus")
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# Xilinx Kintex7
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platforms.append("genesys2")
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platforms.append("kc705")
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platforms.append("kx2")
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platforms.append("nereid")
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# Xilinx Virtex7
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platforms.append("vc707")
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# Xilinx Kintex Ultrascale
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platforms.append("kcu105")
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# Xilinx Zynq Ultrascale+
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platforms.append("zcu104")
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# Xilinx Virtex Ultrascale+
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platforms.append("vcu118")
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# Intel Cyclone4
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platforms.append("de0nano")
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platforms.append("de2_115")
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# Intel Cyclone5
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platforms.append("de1soc")
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platforms.append("de10nano")
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# Intel Max10
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platforms.append("de10lite")
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# Lattice iCE40
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platforms.append("fomu_evt")
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platforms.append("fomu_hacker")
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platforms.append("fomu_pvt")
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platforms.append("tinyfpga_bx")
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# Lattice MachXO2
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platforms.append("machxo3")
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# Lattice ECP3
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platforms.append("versa_ecp3")
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# Lattice ECP5
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platforms.append("ecp5_evn")
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platforms.append("hadbadge")
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platforms.append("orangecrab_r0_1")
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platforms.append("orangecrab_r0_2")
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platforms.append("trellisboard")
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platforms.append("ulx3s")
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platforms.append("versa_ecp5")
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platforms.append("colorlight_5a_75b")
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# Microsemi PolarFire
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platforms.append("avalanche")
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for name in platforms:
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with self.subTest(platform=name):
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cmd = """\
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litex_boards/targets/simple.py litex_boards.platforms.{} \
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--no-compile-software \
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--no-compile-gateware \
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--uart-name="stub" \
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""".format(name)
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subprocess.check_call(cmd, shell=True)
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