127 lines
4.9 KiB
Python
127 lines
4.9 KiB
Python
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("T28"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("V19"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("U30"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("U29"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("V20"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("V26"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("W24"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("W23"), IOStandard("LVCMOS33")),
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("cpu_reset_n", 0, Pins("R19"), IOStandard("LVCMOS33")),
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("user_btn_c", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("user_btn_d", 0, Pins("M19"), IOStandard("LVCMOS33")),
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("user_btn_l", 0, Pins("M20"), IOStandard("LVCMOS33")),
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("user_btn_r", 0, Pins("C19"), IOStandard("LVCMOS33")),
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("user_btn_u", 0, Pins("B19"), IOStandard("LVCMOS33")),
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("user_sw", 0, Pins("G19"), IOStandard("LVCMOS12")),
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("user_sw", 1, Pins("G25"), IOStandard("LVCMOS12")),
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("user_sw", 2, Pins("H24"), IOStandard("LVCMOS12")),
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("user_sw", 3, Pins("K19"), IOStandard("LVCMOS12")),
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("user_sw", 4, Pins("N19"), IOStandard("LVCMOS12")),
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("user_sw", 5, Pins("P19"), IOStandard("LVCMOS12")),
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("user_sw", 6, Pins("P26"), IOStandard("LVCMOS33")),
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("user_sw", 7, Pins("P27"), IOStandard("LVCMOS33")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("serial", 0,
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Subsignal("tx", Pins("Y23")),
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Subsignal("rx", Pins("Y20")),
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IOStandard("LVCMOS33")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11",
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"Y10 Y11 AB8 AA8 AB12 AA12 AH9"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AE9 AB10 AC11"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AE11"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AF11"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AG13"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AH12"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("AD4 AF3 AH4 AF8"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AD3 AC2 AC1 AC5 AC4 AD6 AE6 AC7",
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"AF2 AE1 AF1 AE4 AE3 AE5 AF5 AF6",
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"AJ4 AH6 AH5 AH2 AJ2 AJ1 AK1 AJ3",
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"AF7 AG7 AJ6 AK6 AJ8 AK8 AK5 AK4"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AD2 AG4 AG2 AH7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AD1 AG3 AH1 AJ7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AB9"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AC9"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AJ9"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AK9"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AG5"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("AE10")),
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Subsignal("rx", Pins("AG10")),
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IOStandard("LVCMOS15")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("AH24"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("AK16"), IOStandard("LVCMOS18")),
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Subsignal("mdio", Pins("AG12"), IOStandard("LVCMOS15")),
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Subsignal("mdc", Pins("AF12"), IOStandard("LVCMOS15")),
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Subsignal("rx_ctl", Pins("AH11"), IOStandard("LVCMOS15")),
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Subsignal("rx_data", Pins("AJ14 AH14 AK13 AJ13"), IOStandard("LVCMOS15")),
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Subsignal("tx_ctl", Pins(" AK14"), IOStandard("LVCMOS15")),
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Subsignal("tx_data", Pins("AJ12 AK11 AJ11 AK10"), IOStandard("LVCMOS15")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("HPC", {
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"DP0_C2M_P": "Y2",
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"DP0_C2M_N": "Y1",
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"DP0_M2C_P": "AA4",
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"DP0_M2C_N": "AA3",
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"GBTCLK0_M2C_P": "L8",
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"GBTCLK0_M2C_N": "L7",
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}
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
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except ConstraintError:
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pass
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