88 lines
3.2 KiB
Python
Executable File
88 lines
3.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import quicklogic_quickfeather
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, with_eos_s3=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if with_eos_s3:
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# Use clocks generated by the EOS-S3 CPU.
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self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
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self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
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else:
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# Use clocks generated by the qlal4s3b_cell_macro.
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class Open(Signal): pass
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self.specials += Instance("qlal4s3b_cell_macro",
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o_Sys_Clk0 = self.cd_sys.clk,
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o_Sys_Clk0_Rst = self.cd_sys.rst,
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o_Sys_Clk1 = Open(),
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o_Sys_Clk1_Rst = Open(),
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(10e6), with_led_chaser=True, with_gpioin=True, **kwargs):
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platform = quicklogic_quickfeather.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["cpu_type"] = kwargs.get("cpu_type", None)
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kwargs["with_uart"] = False
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QuickLogic QuickFeather",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos-s3")
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# GPIOIn -> interrupt test
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if with_gpioin:
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self.submodules.gpio = GPIOIn(
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pads = platform.request_all("user_btn_n"), with_irq=True)
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self.irq.add("gpio", use_loc_if_exists=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Quicklogic QuickFeather")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, compile_software=False)
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builder.build(run=args.build)
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if __name__ == "__main__":
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main()
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