143 lines
4.9 KiB
Python
143 lines
4.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Lucas Teske <lucas@teske.com.br>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Muselab IceSugar Pro PCB and IOs have been documented by @wuxx
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# https://github.com/wuxx/icesugar-pro
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import EcpDapProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# Led
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("user_led_n", 0, Pins("B11"), IOStandard("LVCMOS33")), # Red
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("user_led_n", 1, Pins("A11"), IOStandard("LVCMOS33")), # Green
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("user_led_n", 2, Pins("A12"), IOStandard("LVCMOS33")), # Blue
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("rgb_led", 0,
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Subsignal("r", Pins("B11")),
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Subsignal("g", Pins("A11")),
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Subsignal("b", Pins("A12")),
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IOStandard("LVCMOS33"),
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),
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# Reset button
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("cpu_reset_n", 0, Pins("L14"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
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# Serial
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("serial", 0, # iCELink
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Subsignal("tx", Pins("B9")),
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Subsignal("rx", Pins("A9")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash (W25Q256JV (32MB))
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("spiflash", 0,
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Subsignal("cs_n", Pins("N8")),
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# https://github.com/m-labs/nmigen-boards/pull/38
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("T8")),
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Subsignal("miso", Pins("T7")),
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IOStandard("LVCMOS33"),
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),
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# SDRAM (IS42S16160B (32MB))
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("sdram_clock", 0, Pins("R15"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"H15 B13 B12 J16 J15 R12 K16 R13",
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"T13 K15 A13 R14 T14")),
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Subsignal("dq", Pins(
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"F16 E15 F15 D14 E16 C15 D16 B15",
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"R16 P16 P15 N16 N14 M16 M15 L15")),
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Subsignal("we_n", Pins("A15")),
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Subsignal("ras_n", Pins("B16")),
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Subsignal("cas_n", Pins("G16")),
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Subsignal("cs_n", Pins("A14")),
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Subsignal("cke", Pins("L16")),
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Subsignal("ba", Pins("G15 B14")),
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Subsignal("dm", Pins("C16 T15")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("J12")),
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Subsignal("mosi", Pins("H12"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins("G12"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins("K12"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("clk", Pins("J12")),
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Subsignal("cmd", Pins("H12"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("K12 L12 F12 G12"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33")
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),
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# GPDI
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("gpdi", 0,
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Subsignal("clk_p", Pins("E2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("clk_n", Pins("D3"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("G1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data0_n", Pins("F1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("J1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data1_n", Pins("H2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data2_p", Pins("L1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data2_n", Pins("K2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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),
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# RMII Ethernet PHY (WaveShare Board)
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# Assumed to be modified to be PMOD-compatible (TX1 tied to MDIO)
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# Position is P4 header "top half" (toward the GPDI connector)
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("D5")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rx_data", Pins("D4 C3")),
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Subsignal("crs_dv", Pins("C4")),
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Subsignal("tx_en", Pins("E4")),
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Subsignal("tx_data", Pins("E3 R7")),
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IOStandard("LVCMOS33"),
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),
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]
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# from colorlight_i5.py adapted to icesugar pro
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# https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-pinmap.png
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_connectors = [
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("pmode", "N3 M2 L2 G2 P1 N1 M1 K1"),
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("pmodf", "T6 R5 R4 R3 P7 R6 T4 T3"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="trellis"):
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device = "LFE5U-25F-6BG256C"
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io = _io
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connectors = _connectors
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LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
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def create_programmer(self):
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return EcpDapProgrammer()
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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