mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
204 lines
8.5 KiB
Python
Executable file
204 lines
8.5 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Andelf <andelf@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.soc.cores.clock.gowin_gw2a import GW2APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.video import *
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from litex_boards.platforms import lckfb_ljpi
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from litedram.modules import MT41J128M16
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from litedram.phy import GW2DDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_hdmi=False, with_dram=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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if with_dram:
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self.cd_init = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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if with_hdmi:
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk50 = platform.request("clk50")
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rst_n = platform.request("rst_n")
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# Power on reset (the onboard POR is not aware of reprogramming)
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk50)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | ~rst_n)
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pll.register_clkin(clk50, 50e6)
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if with_dram:
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# 2:1 clock needed for DDR
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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self.specials += [
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Instance("DHCEN",
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i_CLKIN = self.cd_sys2x_i.clk,
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i_CE = self.stop,
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o_CLKOUT = self.cd_sys2x.clk),
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Instance("CLKDIV",
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p_DIV_MODE = "2",
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i_CALIB = 0,
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i_HCLKIN = self.cd_sys2x.clk,
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i_RESETN = ~self.reset,
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o_CLKOUT = self.cd_sys.clk),
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]
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# Init clock domain
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self.comb += self.cd_init.clk.eq(clk50)
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self.comb += self.cd_init.rst.eq(pll.reset)
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else:
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset)
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# Video PLL
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if with_hdmi:
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self.video_pll = video_pll = GW2APLL(devicename=platform.devicename, device=platform.device)
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video_pll.register_clkin(clk50, 50e6)
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video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=1e-3)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE = "5",
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i_RESETN = 1, # Disable reset signal.
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i_CALIB = 0, # No calibration.
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i_HCLKIN = self.cd_hdmi5x.clk,
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="gowin", sys_clk_freq=50e6,
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with_spi_flash = False,
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with_led_chaser = True,
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with_buttons = True,
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with_video_terminal = False,
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with_video_colorbars = False,
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**kwargs):
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platform = lckfb_ljpi.Platform(toolchain=toolchain)
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with_hdmi = with_video_terminal or with_video_colorbars
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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assert not (toolchain == "apicula" and with_dram)
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self.crg = _CRG(platform, sys_clk_freq, with_hdmi=with_hdmi, with_dram=with_dram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LCKFB LJPI", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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# if not self.integrated_main_ram_size:
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if with_dram:
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self.ddrphy = GW2DDRPHY(
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pads = platform.request("ddram"),
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sys_clk_freq = sys_clk_freq
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)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64JV as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Video ------------------------------------------------------------------------------------
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if with_hdmi:
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hdmi_pads = platform.request("hdmi")
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self.videophy = VideoHDMIPHY(hdmi_pads, clock_domain="hdmi")
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if with_video_terminal:
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# self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@75Hz", clock_domain="hdmi")
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if with_video_colorbars:
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# self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# self.add_video_colorbars(phy=self.videophy, timings="800x600@75Hz", clock_domain="hdmi")
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self.add_video_colorbars(phy=self.videophy, timings="1024x768@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led"),
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sys_clk_freq = sys_clk_freq
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn_n"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=lckfb_ljpi.Platform, description="LiteX SoC on LCKFB LJPI.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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parser.add_target_argument("--prog-kit", default="gpwin", help="Programmer select from Gowin/openFPGALoader.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_video_colorbars = args.with_video_colorbars,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"))
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if __name__ == "__main__":
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main()
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