150 lines
4.5 KiB
Python
150 lines
4.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("B1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C1"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("D1"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("B1"), IOStandard("LVCMOS33")),
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Subsignal("g", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("b", Pins("D1"), IOStandard("LVCMOS33")),
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),
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# SDRAM
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("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"R14 M14 L14 L13 G12 G13 G14 G15",
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"F12 F13 T15 F14 E14")),
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Subsignal("ba", Pins("T14 T13")),
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Subsignal("cs_n", Pins("G16")),
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Subsignal("cke", Pins("F15")),
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Subsignal("ras_n", Pins("J16")),
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Subsignal("cas_n", Pins("K16")),
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Subsignal("we_n", Pins("L15")),
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Subsignal("dq", Pins(
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"R15 R16 P16 P15 N16 N14 M16 M15",
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"E15 D16 D14 C16 B16 C14 C15 B15")),
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Subsignal("dm", Pins("L16 E16")),
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IOStandard("LVTTL33")
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),
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# VGA
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("vga", 0,
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Subsignal("r", Pins("J3")),
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Subsignal("g", Pins("K3")),
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Subsignal("b", Pins("H2")),
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Subsignal("hsync", Pins("J1")),
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Subsignal("vsync", Pins("J2")),
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IOStandard("LVCMOS33")
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),
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# Differential Data Multiple Interface
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("ddmi", 0,
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Subsignal("clk_p", Pins("R5"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("P4"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("P1"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data2_p", Pins("N1"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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),
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# USB-C
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("usb", 0,
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Subsignal("d_p", Pins("T6")),
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Subsignal("d_n", Pins("R6")),
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Subsignal("pullup", Pins("R7")),
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IOStandard("LVCMOS33")
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),
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# USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("PMODB:0 PMODB:2")),
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Subsignal("dm", Pins("PMODB:1 PMODB:3")),
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#Subsignal("dp", Pins("F2 PMODB:0")),
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#Subsignal("dm", Pins("E1 PMODB:1")),
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IOStandard("LVCMOS33")
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),
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# UART PMOD
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("serial", 0,
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Subsignal("tx", Pins("PMODA:1")),
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Subsignal("rx", Pins("PMODA:2")),
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IOStandard("LVCMOS33")
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),
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# SPI
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("spiflash", 0,
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Subsignal("cs_n", Pins("N8"), Misc("PULLMODE=UP")),
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Subsignal("clk", Pins("N9")),
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Subsignal("miso", Pins("T7"), Misc("PULLMODE=UP")),
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Subsignal("mosi", Pins("T8"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=SLOW"),
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IOStandard("LVCMOS33"),
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),
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]
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_io_v1 = [
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# SD card w/ SD-mode interface
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("sdcard", 0,
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Subsignal("cd", Pins("A13")),
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Subsignal("clk", Pins("D6")),
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Subsignal("cmd", Pins("C6")),
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Subsignal("data", Pins("E6 B13 B12 B6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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("PMODA", "A2 A3 A4 A5 B3 B4 B5 A6"),
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("PMODB", "A12 A11 B11 B10 A9 A10 B8 B9"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeECP5Platform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v1", device="45F", toolchain="trellis", **kwargs):
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assert revision in ["v1", "v2"]
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assert device in ["12F", "25F", "45F", "85F"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v1": io += _io_v1
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LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, cable):
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return OpenFPGALoader(cable=cable)
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def do_finalize(self, fragment):
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LatticeECP5Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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