264 lines
8.3 KiB
Python
Executable File
264 lines
8.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 David Shah <dave@ds0.me>
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# License: BSD
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import re, sys
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"""
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This is a script to parse a Xilinx XDC file and produce a LiteX board Python file.
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It has been tested on the Alveo U250 XDC file from
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https://www.xilinx.com/member/forms/download/design-license.html?cid=41a21059-3945-404a-a349-35140c65291a&filename=xtp573-alveo-u250-xdc.zip
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The "extras" section and name parsing rules will need modification to support other boards.
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"""
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extras = {
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("ddram", "dm"): [("IOStandard", "POD12_DCI")],
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("ddram", "dq"): [
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("IOStandard", "POD12_DCI"),
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("Misc", "PRE_EMPHASIS=RDRV_240"),
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("Misc", "EQUALIZATION=EQ_LEVEL2"),
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],
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("ddram", "dqs_p"): [
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("IOStandard", "DIFF_POD12"),
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("Misc", "PRE_EMPHASIS=RDRV_240"),
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("Misc", "EQUALIZATION=EQ_LEVEL2"),
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],
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("ddram", "dqs_n"): [
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("IOStandard", "DIFF_POD12"),
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("Misc", "PRE_EMPHASIS=RDRV_240"),
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("Misc", "EQUALIZATION=EQ_LEVEL2"),
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],
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("ddram", "clk_p"): [("IOStandard", "DIFF_SSTL12_DCI")],
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("ddram", "clk_n"): [("IOStandard", "DIFF_SSTL12_DCI")],
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("ddram", "reset_n"): [("IOStandard", "LVCMOS12")],
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("ddram", "*"): [("IOStandard", "SSTL12_DCI")],
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("ddram", ): [("Misc", "SLEW=FAST")],
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("clk300", "*"): [("IOStandard", "DIFF_SSTL12")],
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("cpu_reset", "*"): [("IOStandard", "LVCMOS12")],
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("ddr4_reset_gate", "*"): [("IOStandard", "LVCMOS12")],
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("gpio_msp", "*"): [("IOStandard", "LVCMOS12")],
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("user_led", "*"): [("IOStandard", "LVCMOS12")],
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("dip_sw", "*"): [("IOStandard", "LVCMOS12")],
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("set_w", "*"): [("IOStandard", "LVCMOS12")],
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("pcie_x16", "rst_n"): [("IOStandard", "LVCMOS12")],
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("serial", "*"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "modskll_ls"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "resetl_ls"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "intl_ls"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "lpmode_ls"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "refclk_reset"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "fs0"): [("IOStandard", "LVCMOS12")],
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("qsfp28", "fs1"): [("IOStandard", "LVCMOS12")],
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("i2c", "*"): [("IOStandard", "LVCMOS12")],
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("i2c_main_reset_n", "*"): [("IOStandard", "LVCMOS12")],
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("serial_msp", "*"): [("IOStandard", "LVCMOS12")],
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("user_si570_clock", "*"): [("IOStandard", "DIFF_SSTL12")],
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}
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groups = {}
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ddr4_re = re.compile(r'DDR4_C(\d)_(.*)')
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simple_ports = {
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"CPU_RESET_FPGA": ("cpu_reset", 0),
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"DDR4_RESET_GATE": ("ddr4_reset_gate", 0),
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"GPIO_MSP0": ("gpio_msp", 0),
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"GPIO_MSP1": ("gpio_msp", 1),
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"GPIO_MSP2": ("gpio_msp", 2),
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"GPIO_MSP3": ("gpio_msp", 3),
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"STATUS_LED0_FPGA": ("user_led", 0),
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"STATUS_LED1_FPGA": ("user_led", 1),
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"STATUS_LED2_FPGA": ("user_led", 2),
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"SW_DP0": ("dip_sw", 0),
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"SW_DP1": ("dip_sw", 1),
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"SW_DP2": ("dip_sw", 2),
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"SW_DP3": ("dip_sw", 3),
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"SW_SET1_FPGA": ("set_sw", 0),
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"I2C_MAIN_RESET_B_LS": ("i2c_main_reset_n", 0),
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}
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def permute_dqs(i):
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# Huh?
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if i >= 9:
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return (i - 9) * 2 + 1
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else:
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return i * 2
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def parse_port(port):
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dm = ddr4_re.match(port)
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if dm:
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res = ("ddram", int(dm.group(1)))
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x = dm.group(2)
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if x.startswith("ADR"):
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i = int(x[3:])
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if i == 17:
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return None # not used on included DIMM
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if i == 16:
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s = ("ras_n", )
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elif i == 15:
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s = ("cas_n", )
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elif i == 14:
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s = ("we_n", )
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else:
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s = ("a", i)
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elif x.startswith("BA"):
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s = ("ba", int(x[2:]))
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elif x.startswith("BG"):
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s = ("bg", int(x[2:]))
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elif x.startswith("CK_T"):
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if int(x[4:]) > 0:
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return None # not used on included DIMM
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s = ("clk_p", int(x[4:]))
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elif x.startswith("CK_C"):
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if int(x[4:]) > 0:
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return None # not used on included DIMM
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s = ("clk_n", int(x[4:]))
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elif x.startswith("CKE"):
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if int(x[3:]) > 0:
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return None # not used on included DIMM
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s = ("cke", int(x[3:]))
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elif x.startswith("CS_B"):
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if int(x[4:]) > 0:
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return None # not used on included DIMM
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s = ("cs_n", int(x[4:]))
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elif x.startswith("ODT"):
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if int(x[3:]) > 0:
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return None # not used on included DIMM
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s = ("odt", int(x[3:]))
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elif x in ("ACT_B", "ALERT_B", "EVENT_B", "PAR", "RESET_N"):
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if x == "ALERT_B" or x == "PAR" or x == "EVENT_B":
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return None # not used on included DIMM
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x = x.replace("_B", "_N")
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s = (x.lower(), )
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elif x.startswith("DQS_T"):
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i = permute_dqs(int(x[5:]))
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if i >= 16:
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return None
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s = ("dqs_p", int(i))
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elif x.startswith("DQS_C"):
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i = permute_dqs(int(x[5:]))
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if i >= 16:
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return None
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s = ("dqs_n", int(i))
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elif x.startswith("DQ"):
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if int(x[2:]) >= 64:
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return None
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s = ("dq", int(x[2:]))
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else:
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assert False, port
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return (res, s)
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elif port in simple_ports:
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return (simple_ports[port], (simple_ports[port][0], ))
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elif port.startswith("SYSCLK") and "_300_" in port:
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return (("clk300", int(port[6])), (port[-1].lower(), ))
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elif port.startswith("PEX_"):
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res = ("pcie_x16", 0)
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if port[4:6] == "TX":
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s = ("tx_" + port[-1].lower(), int(port[6:port.rfind('_')]))
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elif port[4:6] == "RX":
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s = ("rx_" + port[-1].lower(), int(port[6:port.rfind('_')]))
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elif port[4:10] == "REFCLK":
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s = ("clk_" + port[-1].lower(), )
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else:
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assert False, port
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return (res, s)
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elif port == "PCIE_PERST_LS":
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return (("pcie_x16", 0), ("rst_n", ))
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elif port.startswith("USB_UART_"):
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# This is from FTDI perspective, we want FPGA perspective
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u = port[-2:].lower()
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return (("serial", 0), ("tx" if u == "rx" else "rx", ))
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elif port.startswith("MGT_SI570_CLOCK"):
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return (("mgt_si570_clock", int(port[15])), (port[-1].lower(), ))
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elif port.startswith("USER_SI570_CLOCK"):
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return (("user_si570_clock", 0), (port[-1].lower(), ))
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elif port.startswith("QSFP"):
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res = ("qsfp28", int(port[4]))
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if port[6:8] == "TX":
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s = ("tx" + port[-1].lower(), int(port[8])-1)
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elif port[6:8] == "RX":
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s = ("rx" + port[-1].lower(), int(port[8])-1)
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elif port[6:11] == "CLOCK":
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s = ("clk_" + port[-1].lower(), )
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elif port.endswith("REFCLK_RESET") or "_FS" in port:
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s = (port[6:].lower(), )
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elif port.endswith("_LS"):
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s = (port.split("_")[1].lower(), )
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else:
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assert False, port
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return (res, s)
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elif port.startswith("I2C_FPGA_"):
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return (("i2c", 0), (port.split("_")[2].lower(), ))
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elif port.endswith("_MSP"):
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return (("serial_msp", 0), (port.split("_")[1].lower()[:-1], ))
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elif port == "No" or port.startswith("VR") or port.startswith("N3") or "SYSMON" in port or port.startswith("TEST"):
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pass
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else:
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assert False, port
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return None
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with open(sys.argv[1], "r") as xf:
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for line in xf:
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if "PACKAGE_PIN" not in line:
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continue
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sl = [x.strip() for x in re.split(r'\s|\[', line.strip(), )]
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sl = [x for x in sl if x != ""]
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pin = sl[sl.index("PACKAGE_PIN") + 1]
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port = sl[sl.index("get_ports") + 1]
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rs = parse_port(port)
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if rs is None:
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continue
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res, sig = rs
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if sig is None:
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groups[res] = pin
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else:
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if res not in groups:
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groups[res] = {}
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if len(sig) == 2:
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if sig[0] not in groups[res]:
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groups[res][sig[0]] = {}
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groups[res][sig[0]][sig[1]] = pin
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else:
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groups[res][sig[0]] = {0: pin}
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def format_extras(items, force_newline = False, indent=" ", lcomma=","):
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extra = "{} \n{}".format(lcomma, indent) if force_newline else "{} ".format(lcomma)
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extra += (", \n{}".format(indent)).join(['{}("{}")'.format(i[0], i[1]) for i in items])
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return extra
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print("_io = [")
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for res, sigs in sorted(groups.items(), key=lambda x: x[0]):
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res_name = res[0]
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res_index = res[1]
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if res_name == "ddram" and res_index > 0:
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res_name = "ddram_ch{}".format(res_index + 1)
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res_index = 0
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print(' ("{}", {}, '.format(res_name, res_index), end='\n' if len(sigs) > 1 else '')
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for sig, pins in sorted(sigs.items(), key=lambda x: x[0]):
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max_idx = max(pins.keys())
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if len(pins) > 8:
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p = ""
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for j in range((len(pins) + 7) // 8):
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p += '\n "{}"{}'.format(" ".join([pins[i] for i in range(j * 8,
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min((j + 1) * 8, max_idx+1))]), "," if j < ((len(pins) + 7) // 8 - 1) else "")
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else:
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p = '"{}"'.format(" ".join([pins[i] for i in range(max_idx+1)]))
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extra = ""
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if (res[0], sig) in extras:
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extra = format_extras(extras[res[0], sig], len(pins) > 8)
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elif (res[0], "*") in extras:
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extra = format_extras(extras[res[0], "*"], len(pins) > 8)
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if len(sigs) == 1:
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print('Pins({}){}'.format(p, extra), end='')
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else:
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print(' Subsignal("{}", Pins({}){}),'.format(sig, p, extra))
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if (res[0], ) in extras:
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print(format_extras(extras[res[0], ], False, " ", " "))
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print(' ),' if len(sigs) > 1 else '),')
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print("]")
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