166 lines
6.4 KiB
Python
166 lines
6.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Dolu1990 <charles.papon.90@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.efinix.platform import EfinixPlatform
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from litex.build.efinix import EfinixProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk25", 0, Pins("L17"), IOStandard("1.8_V_LVCMOS")),
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("clk100", 0, Pins("U4"), IOStandard("3.3_V_LVCMOS")),
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("clketh", 0, Pins("A14"), IOStandard("1.8_V_LVCMOS")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins(" E9")),
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Subsignal("rx", Pins("E10")),
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IOStandard("3.3_V_LVTTL"),
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Misc("WEAK_PULLUP"),
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),
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# Buttons.
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("user_btn", 0, Pins("U19"), IOStandard("3.3_V_LVCMOS")),
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# DRAM.
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("dram_pll_refclk", 0, Pins("XXX"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
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# SDCard.
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("spisdcard", 0,
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Subsignal("clk", Pins(" C9")),
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Subsignal("mosi", Pins("C10")),
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Subsignal("cs_n", Pins(" A9")),
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Subsignal("miso", Pins(" B9")),
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IOStandard("3.3_V_LVCMOS"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("B9 B10 A8 A9")),
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Subsignal("cmd", Pins("C10")),
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Subsignal("clk", Pins("C9")) , #, Misc("SLEWRATE=1"), Misc("DRIVE_STRENGTH=16")
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IOStandard("3.3_V_LVTTL"),
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),
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# ETH.
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("eth_clocks", 0,
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Subsignal("tx", Pins("C17")),
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Subsignal("rx", Pins("D15")),
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IOStandard("1.8_V_LVCMOS"),
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Misc("SLEWRATE=1"),
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Misc("DRIVE_STRENGTH=16")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("D10"), IOStandard("3.3_V_LVCMOS")),
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Subsignal("int_n", Pins("B11"), IOStandard("3.3_V_LVCMOS")),
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Subsignal("mdio", Pins("B14")),
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Subsignal("mdc", Pins("B19")),
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Subsignal("rx_ctl", Pins("H18")),
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Subsignal("rx_data", Pins("A18 A19 D16 D17")),
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Subsignal("tx_ctl", Pins("B20")),
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Subsignal("tx_data", Pins("B17 A16 A17 C19")),
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IOStandard("1.8_V_LVCMOS"),
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Misc("SLEWRATE=1"),
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Misc("DRIVE_STRENGTH=16")
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),
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# FAN.
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("fan_speed_control", 0, Pins("T19"), IOStandard("3.3_V_LVCMOS")),
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]
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# Bank voltage ---------------------------------------------------------------------------------------
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_bank_info = [
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("2A" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2A_MODE_SEL"/>
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("2B" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2B_MODE_SEL"/>
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("2C" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2C_MODE_SEL"/>
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("2D" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2D_MODE_SEL"/>
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("2E" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2E_MODE_SEL"/>
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("4A_4B" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4A_4B_MODE_SEL"/>
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("4C" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4C_MODE_SEL"/>
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("4D" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4D_MODE_SEL"/>
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("BL2_BL3" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("BR0" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="BR0_MODE_SEL"/>
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("BR3_BR4" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("TL1_TL5" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("TR0" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR0_MODE_SEL"/>
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("TR1" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR1_MODE_SEL"/>
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("TR2" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR2_MODE_SEL"/>
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod0", "G15 G16 F16 F17 G17 A11 A13 A12"),
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("pmod1", "B12 C14 C13 C12 D12 F12 D13 E13"),
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("pmod2", "E14 E16 F13 E15 F14 E11 F11 D11"),
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["p1",
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"---", # 0
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# 3V3 5V GND GND GND GND GND GND ↓
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"--- B21 --- A21 --- --- C22 E21 B22 D21 --- --- B23 F21 A22 F22 --- --- D22 G21",
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# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ↑
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# 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 ↓
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"D23 G22 --- --- F23 H20 E23 G20 --- --- H22 K23 H23 L23 --- --- L19 M21 M19 M22",
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# GND GND GND GND GND GND ↑
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],
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]
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# PMODS --------------------------------------------------------------------------------------------
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def raw_pmod_io(pmod):
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return [(pmod, 0, Pins(" ".join([f"{pmod}:{i:d}" for i in range(8)])), IOStandard("3.3_V_LVTTL_/_LVCMOS"))]
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def jtag_pmod_io(pmod):
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return [
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("usb_uart", 0,
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Subsignal("tck", Pins(f"{pmod}:0")),
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Subsignal("tdi", Pins(f"{pmod}:1")),
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Subsignal("tdo", Pins(f"{pmod}:2")),
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Subsignal("tms", Pins(f"{pmod}:3")),
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IOStandard("3.3_V_LVCMOS")
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),
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]
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def hdmi_px(px):
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return [
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("hdmi_i2c", 0,
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Subsignal("sda", Pins(f"{px}:26")),
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Subsignal("scl", Pins(f"{px}:28")),
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IOStandard("1.8_V_LVCMOS"),
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Misc("WEAK_PULLUP"),
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Misc("SCHMITT_TRIGGER"),
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),
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("hdmi_data", 0,
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Subsignal("clk", Pins(f"{px}:4")),
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Subsignal("de", Pins(f"{px}:33")),
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Subsignal("d", Pins(f"{px}:31 {px}:27 {px}:25 {px}:21 {px}:19 {px}:15 {px}:13 {px}:9 {px}:7 {px}:2 {px}:8 {px}:10 {px}:14 {px}:16 {px}:20 {px}:22")),
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IOStandard("1.8_V_LVCMOS")
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),
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("hdmi_sync", 0,
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Subsignal("hsync", Pins(f"{px}:37")),
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Subsignal("vsync", Pins(f"{px}:39")),
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IOStandard("1.8_V_LVCMOS")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(EfinixPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="efinity"):
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EfinixPlatform.__init__(self, "Ti375C529C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
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def create_programmer(self):
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return EfinixProgrammer()
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def do_finalize(self, fragment):
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EfinixPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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