153 lines
5.0 KiB
Python
153 lines
5.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Fabien Caura <fabien@acathla.tk>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxSpartan6Platform
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from litex.build.xilinx.programmer import XC3SProg
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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# Serial.
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("serial", 1,
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Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("mosi", Pins("P64")),
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Subsignal("miso", Pins("P65"), Misc("PULLUP")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("dq", Pins("P64", "P65")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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# SDR SDRAM.
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("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins(
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"P140 P139 P138 P137 P46 P45 P44",
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"P43 P41 P40 P141 P35 P34"
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)),
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Subsignal("ba", Pins("P143 P142")),
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Subsignal("cs_n", Pins("P1")),
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Subsignal("cke", Pins("P33")),
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Subsignal("ras_n", Pins("P2")),
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Subsignal("cas_n", Pins("P5")),
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Subsignal("we_n", Pins("P6")),
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Subsignal("dq", Pins(
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"P9 P10 P11 P12 P14 P15 P16 P8",
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"P21 P22 P23 P24 P26 P27 P29 P30"
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)),
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Subsignal("dm", Pins("P7 P17")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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)
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
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("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"),
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("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
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# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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]
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# Extensions --------------------------------------------------------------------------------------
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# Arcade MegaWing V1.3 pinout
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_arcade_megawing = [
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# VGA.
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("vga", 0,
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Subsignal("r", Pins("C:4 C:5 C:6 C:7")),
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Subsignal("g", Pins("B:4 B:5 B:6 B:7")),
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Subsignal("b", Pins("B:0 B:1 B:2 B:3")),
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Subsignal("vsync_n", Pins("C:2")),
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Subsignal("hsync_n", Pins("C:3")),
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IOStandard("LVCMOS33")
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),
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# Buttons.
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("buttons", 0,
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Subsignal("up", Pins("C:8")),
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Subsignal("down", Pins("C:10")),
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Subsignal("left", Pins("C:11")),
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Subsignal("right", Pins("C:13")),
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IOStandard("LVCMOS33")
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),
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# Joysticks ports.
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("joy", 0,
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Subsignal("up", Pins("C:8")),
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Subsignal("down", Pins("C:10")),
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Subsignal("left", Pins("C:11")),
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Subsignal("right", Pins("C:13")),
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Subsignal("fire1", Pins("C:9")),
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Subsignal("fire2", Pins("C:15")),
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IOStandard("LVCMOS33")
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),
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("joy", 1,
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Subsignal("up", Pins("B:12")),
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Subsignal("down", Pins("B:14")),
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Subsignal("left", Pins("B:15")),
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Subsignal("right", Pins("A:1")),
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Subsignal("fire1", Pins("B:13")),
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Subsignal("fire2", Pins("A:3")),
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IOStandard("LVCMOS33")
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),
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# PS2 ports.
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("ps2", 0,
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Subsignal("clk", Pins("C:1")),
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Subsignal("data", Pins("C:0")),
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IOStandard("LVCMOS33")
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),
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("ps2", 1,
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Subsignal("clk", Pins("A:13")),
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Subsignal("data", Pins("A:12")),
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IOStandard("LVCMOS33")
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),
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# Leds.
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("amw_user_led", 0, Pins("A:7"), IOStandard("LVCMOS33")),
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("amw_user_led", 1, Pins("A:6"), IOStandard("LVCMOS33")),
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("amw_user_led", 2, Pins("A:5"), IOStandard("LVCMOS33")),
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("amw_user_led", 3, Pins("A:4"), IOStandard("LVCMOS33")),
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# Reset button.
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("reset_button", 0, Pins("P85"), IOStandard("LVCMOS33") )
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxSpartan6Platform):
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default_clk_name = "clk32"
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default_clk_period = 1e9/32e6
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def __init__(self, toolchain="ise"):
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XilinxSpartan6Platform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
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def do_finalize(self, fragment):
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XilinxSpartan6Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)
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