151 lines
6.5 KiB
Python
151 lines
6.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Enjoy-Digital <enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeNexusPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# 5. CertusPro-NX Clock Sources
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("clk125", 0, Pins("N25"), IOStandard("LVCMOS33")), # JP15: open
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("clk12", 0, Pins("R4"), IOStandard("LVCMOS33")), # JP6: close
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("clkresv", 0, Pins("R6"), IOStandard("LVCMOS33")), # DNI, JP18: open
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# Disable Clk Signals
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("resv_clk_dis", 0, Pins("R7"), IOStandard("LVCMOS33")),
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("clk125_clk_dis", 0, Pins("J23"), IOStandard("LVCMOS33")),
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# 7.2. General Purpose Push Buttons - all logic zero when pressed
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("programn", 0, Pins("G4"), IOStandard("LVCMOS18")), # SW2
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("user_btn", 0, Pins("J5"), IOStandard("LVCMOS18")), # SW1
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("user_btn", 1, Pins("J2"), IOStandard("LVCMOS18")), # SW4
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("user_btn", 2, Pins("J3"), IOStandard("LVCMOS18")), # SW5
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# 7.1. DIP Switch
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("user_dip_btn", 0, Pins("K8"), IOStandard("LVCMOS18")),
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("user_dip_btn", 1, Pins("K7"), IOStandard("LVCMOS18")),
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("user_dip_btn", 2, Pins("K6"), IOStandard("LVCMOS18")),
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("user_dip_btn", 3, Pins("K4"), IOStandard("LVCMOS18")),
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("user_dip_btn", 4, Pins("K3"), IOStandard("LVCMOS18")),
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("user_dip_btn", 5, Pins("K2"), IOStandard("LVCMOS18")),
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("user_dip_btn", 6, Pins("J7"), IOStandard("LVCMOS18")),
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("user_dip_btn", 7, Pins("J6"), IOStandard("LVCMOS18")),
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# 6.1 UART Topology (JP1/JP2: close, JP4/JP5: open)
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("serial", 0,
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Subsignal("rx", Pins("L2")),
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Subsignal("tx", Pins("L1")),
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IOStandard("LVCMOS33")
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),
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# 7.3. General Purpose LEDs (Inverted)
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("user_led", 0, Pins("N5"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 1, Pins("N6"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 2, Pins("N7"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 3, Pins("N8"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 4, Pins("L6"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 5, Pins("N9"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 6, Pins("L8"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 7, Pins("M9"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 8, Pins("N1"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 9, Pins("N2"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 10, Pins("N3"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 11, Pins("M1"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 12, Pins("M2"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 13, Pins("M3"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 14, Pins("L3"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 15, Pins("N4"), IOStandard("LVCMOS33")), # Bank 1 Yellow
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("user_led", 16, Pins("T4"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 17, Pins("T5"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 18, Pins("T6"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 19, Pins("T7"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 20, Pins("U8"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 21, Pins("T8"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 22, Pins("R9"), IOStandard("LVCMOS33")), # Bank 1 Red
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("user_led", 23, Pins("P9"), IOStandard("LVCMOS33")), # Bank 1 Red
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# 6.1 I2C Topology (connected to the FTDI with JP4/JP5
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("i2c", 0,
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Subsignal("scl", Pins("M7")),
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Subsignal("sda", Pins("M6")),
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IOStandard("LVCMOS33"),
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),
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# 6.3 SPI Topology
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("spiflash", 0,
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Subsignal("cs_n", Pins("H3")),
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Subsignal("clk", Pins("G6")),
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Subsignal("mosi", Pins("H7")),
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Subsignal("miso", Pins("H6")),
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Subsignal("wp", Pins("K5")),
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Subsignal("hold", Pins("H4")),
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IOStandard("LVCMOS18")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("H3")),
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Subsignal("clk", Pins("G6")),
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Subsignal("dq", Pins("H7 H6 K5 H4")),
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IOStandard("LVCMOS18")
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("V18 W19 AB19 AB20 AB21 AB18 AA17 W18"), IOStandard("LVCMOS18H")),
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Subsignal("rwds", Pins("V19"), IOStandard("LVCMOS18H")),
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Subsignal("cs_n", Pins("AA18"), IOStandard("LVCMOS18H")),
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Subsignal("rst_n", Pins("AB17"), IOStandard("LVCMOS18H")),
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Subsignal("clk", Pins("Y19"), IOStandard("LVDS")),
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# Subsignal("clk_n", Pins("Y18"), IOStandard("LVDS")),
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Misc("SLEWRATE=FAST")
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),
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("hyperram", 1,
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Subsignal("dq", Pins("V22 AA20 V21 U21 U20 Y22 AA22 AA21"), IOStandard("LVCMOS18H")),
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Subsignal("rwds", Pins("Y21"), IOStandard("LVCMOS18H")),
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Subsignal("cs_n", Pins("AA19"), IOStandard("LVCMOS18H")),
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Subsignal("rst_n", Pins("U18"), IOStandard("LVCMOS18H")),
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Subsignal("clk", Pins("W22"), IOStandard("LVDS")),
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# Subsignal("clk_n", Pins("W21"), IOStandard("LVDS")),
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Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Table 6.2 PMOD Header
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# PMOD signal number:
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# 1 2 3 4 7 8 9 10
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("PMOD0", "Y1 W2 V3 V1 Y2 W3 W1 V2"), # J5
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("PMOD1", "V7 V6 V5 V4 V8 W7 W6 W5"), # J4
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("PMOD2", "AA4 AB3 AA2 AA1 W4 Y4 AB2 AB1"), # J6
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# FIXME SMA Header, FMC, TP and RPi Board header
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeNexusPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
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assert device in ["LFCPNX"]
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LatticeNexusPlatform.__init__(self, device + "-100-9LFG672C", _io, _connectors, toolchain=toolchain, **kwargs)
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# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
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self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
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# Evaluation mode (with free license)
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self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
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def create_programmer(self):
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return OpenFPGALoader()
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def do_finalize(self, fragment):
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LatticeNexusPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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